Mahadevan K. Iyer

Modeling of simultaneous switching noise in high speed systems

Simultaneous switching noise (SSN) has become a major bottleneck in high speed digital design. For future systems, modeling SSN can be complex: due to the thousands of interconnects that need to be analyzed. This is because a system level modeling approach is necessary that combines the chip, package and board level interactions. This paper presents an efficient method to model the SSN for high speed systems by developing circuit models for the planes and interconnections that can be combined using superposition theory. This approximation is valid at frequencies where skin effect is dominant. Simulation results are compared with the measurements on a test vehicle, verifying the validity of the method. In addition a system has been simulated to compute SSN, showing the application of this method for complex systems.

Three-dimensional system-in-package using stacked silicon platform technology

In this paper, a novel method of fabricating three-dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP.

Analysis of noise coupling from a power distribution network to signal traces in high-speed multilayer printed circuit boards

As layout density increases in highly integrated multilayer printed circuit boards (PCBs), the noise that exists in the power distribution network (PDN) is increasingly coupled to the signal traces, and precise modeling to describe the coupling phenomenon becomes necessary. This paper presents a model to describe noise coupling between the power/ground planes and signal traces in multilayer systems. An analytical model for the coupling has been successfully derived, and the coupling mechanism was rigorously analyzed and clarified. Wave equations for a signal trace with power/ground noise were solved by imposing boundary conditions. Measurements in both the frequency and time domains have been conducted to confirm the validity of the proposed model.

Chip-last Embedded Active for System-On-Package (SOP)

Embedded active technology, in which thinned active chips are directly buried into a core or high-density-interconnect layers, is gaining more interest for ultra-miniaturization, increased functionality and better performance of SOP (system-on-package). In this study, chip-last embedded active concept is proposed to address some of process and reliability issues that current chip-first and chip-middle embedded active approaches have. The detailed process development for the first prototype of chip-last embedded active is described in this paper.

Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multilayer packages and PCBs

The authors introduced a model of simultaneous switching noise (SSN) coupling between the power/ground plane cavities through cutouts in high-speed and high-density multilayer pack-ages and printed circuit boards (PCBs). Usually, the cutouts are used in multilayer plane structures to isolate the SSN of noisy digital circuits from sensitive analog circuits or to provide multiple voltage levels. The noise-coupling model is expressed in terms of the transfer impedance. The proposed modeling and analysis results are compared with measured data up to 10 GHz to demonstrate the validity of the model. It is demonstrated that the cutout is the major gate for SSN coupling between the plane cavities, and that substantial SSN coupling occurs between the plane cavities through the cutout at the resonant frequencies of the plane cavities. The coupling mechanism and characteristics of the noise coupling, from which a method of suppression of the SSN coupling evaluated was also analyzed and discussed. Proper positioning of the cutout and the devices at each plane cavity achieves significant noise suppression at certain resonant frequencies. The suggested suppression method of the SSN coupling was successfully proved by frequency domain measurement and time domain analysis.

Physics based modeling of simultaneous switching noise in high speed systems

Simultaneous Switching Noise (SSN) has become a major bottleneck in high speed digital design. For future systems, modeling SSN can be complex due to the thousands of interconnects that need to be analyzed. This is because a system level modeling approach is necessary that combines the chip, package and board level interactions. This paper presents an efficient method to model the SSN for high speed systems by developing circuit models for the planes and interconnections that can be combined using superposition. This approximation is valid at frequencies where skin effect is dominant. Simulation results are compared with the measurements on a Test Vehicle, verifying the validity of the method.

Electrochemical Biosensors and Microfluidics in Organic System-on-Package Technology

A nanobioelectronic system-on-package (SOP) with integrated electrochemical sensors, microfluidic channels and microneedles was demonstrated with organic compatible processes. A novel amperometric glucose sensor based on carbon nanotubes/glassy carbon working electrodes and glucose oxidase enzyme encapsulated in a sol-gel derived zirconia/nafion matrix was developed to demonstrate the biosensing. The sol-gel chemistry provides an attractive way to immobilize the sensitive biomolecules on the electrode at low temperatures. The amperometric measurements were carried out with a three-electrode system. SU8 epoxy based thick microfluidic channels were built over the electrode layer and then the enzyme was immobilized, followed by sealing of the channel with a PDMS membrane using a low temperature bonding process (60degC). The enzyme-catalyst reaction was recorded as the release of electrons from the oxidation of glucose into gluconolactone, hydrogen peroxide and subsequently into water. The results indicate that the response time is within few seconds. The current varied from 1 muA to 2.5 muA as the glucose concentration was increased from 5 mM to 20 mM. Finally, a compatible microneedle technology is demonstrated to enable transdermal fluid injection into the device for real-time health monitoring. Nanobio SOP with recent advances in nanobiosensing, nanomedicine, low-cost polymer-based high-density packaging, mixed-signal electronics can lead to the portable, reliable and cost effective biomedical devices of the future.

Thermal design of heat spreader and analysis of thermal interface materials (TIM) for multi-chip package

Industry demand for high power multi-chip packages is increasing to realize multifunctional compact systems. In line with industry requirements a multi-chip package suitable for high performance devices is developed. The package has 1296 I/Os. It is capable of handling 2 GHz signal speed and dissipating 75 W power with an external thermal solution. A concurrent design approach is adopted for the package design. Electrical, thermal, structural issues and assembly, and materials limitations are considered in developing this package. Package level thermal design challenges involve optimization of package structure and selection of stable thermal interface material. As a part of this project, a simulation model of the package along with the external thermal solution is developed and validated by measurements. The optimized heat spreader has been designed by performing a parametric study with the validated model. The type of thermal interface material (TIM) suitable to the package has also been identified by measurements. Desired thermal performance of the package has been achieved through design optimization of the package and selection of suitable TIM. Thermal modeling and measurement methodologies, validation and parametric study results are presented in the paper. Analysis of TIMs and measured thermal performance results of packages assembled with different type of TIMs are also discussed in the paper.

Flipchip bump integrity with copper/ultra low-k dielectrics for fine pitch flipchip packaging

As CMOS transistor scaling proceeds into the deep submicron regime, the number of transistors on high performance, high density ICs is increasing to 45/spl sim/60 millions, in accordance with the historical trend of Moores Law. It is the fundamental motivating factor causing the semiconductor industry to move away from aluminum as interconnect metal with silicon dioxide dielectric between the metal lines, to copper metal and ultra-low-k dielectric materials. Copper reduces the resistance of the metal interconnect lines, while low-k dielectrics reduce the parasitic capacitance between the metal lines: The implementation of copper as an interconnect in conjunction with the ultra low-k materials as interlevel dielectrics (ILDs) or intermetal dielectrics (IMDs) in the fabrication of ULSI circuits has been a main stream especially for high speed devices in the semiconductor community worldwide. The impact of UBM integrity in Cu metallization has been reported and major failure mechanism observed were metal peeling from low-k dielectrics. However investigations reported with different chip ILD/IMD stacking structure and with various UBM metallization and failure analysis of the same particularly with ultra low-k dielectrics are very limited. In this work, two different approaches are studied. One is for chip-side stack structure and another is the application of wafer level packaging technology. The bump failure is found at the chip-side, especially, at the interface of ultra low-k dielectrics materials. To increase the bump adhesion properties, different thickness ILDs were deposited and various adhesion promoter layers were evaluated with several stack structures. In order to achieve the proper solder joint reliability in other approach, wafer level integration techniques were applied. Encapsulation of photosensitive low-k dielectrics and BCB (Benzocyclobutene) were carried out on the Cu/ultra-low-k dielectric wafers. According to the characterization, it gave promising results in view point of adhesion, thus, no more chip-side failure is found. The process, assembly steps, test vehicle design and reliability results, failures and analysis will be reported.

Label-Free Protein Detection by ZnO Nanowire Based Bio-Sensors

There is an increasing demand for portable, reliable, and cost effective bioelectronic systems for applications ranging from clinical diagnosis to homeland security. Conventional detection systems involve labeling the probe molecules, large amount of target molecules to enable detection, and elaborate signal transduction methods. Most of them also have to couple with optical detection equipments that are bulky and expensive. One dimensional (1-D) and two dimensional (2-D) structures such as nanowire, nanobelts and films are capable of detecting the molecular interactions in terms of significant change in their electrical properties leading to ultrahigh sensitivity and easy integration. In this paper, we demonstrate ZnO nanowires based bio-sesnors to detect IgG antibodies. Current-voltage (I-V) and Scanning Electron Microscopy (SEM) characterization were used to monitor the change in the conductivity as well as morphology. By comparing with the reference sample, the specific binding event between anti-IgG and IgG antibodies was detected. The data indicated a conductivity change by more than 12% after the protein hybridization. SEM images confirm the morphological change from reference samples to reacted samples. In addition, same experiment protocols are carried out for ZnO thin film devices. Similar change in I-V characteristics and morphologies are observed. Through this work, we have demonstrated to use ZnO nanowires as building blocks to fabricate bio-sensors which can potentially detect any protein. Conductimetric sensing results in a label-free detection system as it detects the protein hybridization events electrically. It is a cost effective process, which can be exploited further by expanding into arrays and integrating with microfluidics. When integrated on the SOP platform, this technology can lead to portable, reliable and cost effective biosensors with applications in many areas.