Jayawan H. B. Wijekoon

Neuromorphic silicon neuron circuits

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

Integrated circuit implementation of a cortical neuron

This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 mum CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking and bursting firing patterns. The models of various cortical neuron types are obtained in a single circuit, through the adjustment of two biasing voltages, making the circuit suitable for applications in reconfigurable neuromorphic devices that implement biologically plausible spiking neural networks.

Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit

The paper presents a silicon neuron circuit that mimics the behaviour of known classes of biological neurons. The circuit has been designed in a 0.35 mum CMOS technology. The firing patterns of basic cell classes: regular spiking (RS), fast spiking (FS), chattering (CH) and intrinsic bursting (IB) are obtained with a simple adjustment of two biasing voltages. The simulations reveal the potential of the circuit to provide a wide variety of cell behaviours with required accommodation and firing frequency of a given cell type. The neuron consumes only 14 MOSFETs enabling the integration of many neurons in a small silicon area. Hence, the circuit provides a foundation for designing massively parallel analogue neuromorphic networks that closely resemble the circuits of the cortex.

Continuous objective recording of fetal heart rate and fetal movements could reliably identify fetal compromise, which could reduce stillbirth rates by facilitating timely management.

Stillbirth currently affects approximately 1 in every 200 pregnancies in the United Kingdom. Fetuses may exhibit signs of compromise as part of a stress response before stillbirth, including reduced fetal movements (RFM) and fetal heart rate (FHR) alterations. At present, and despite widespread use, current fetal monitoring is not associated with a reduction in perinatal mortality rate (PMR) as signs of fetal compromise are not adequately detected. This may be attributed to inaccuracies resulting from manual interpretation of results or subjective assessment of fetal activity. In addition, signs of compromise often occur only hours or days before fetal death, so may be missed by current monitoring methods, which are performed intermittently. A significant consideration is that correct identification of these signs and consequent intervention can result in the delivery of a healthy baby, thus preventing stillbirth. A hypothesis is presented, proposing prompt detection of fetal compromise with the use of 24-hour continuous objective fetal monitoring. With focus placed on obtaining long-term FHR and fetal movement data, prior interest has been found in developing devices for this purpose. However, introduction into clinical practice has not been achieved. Investigation of the hypothesis will begin with the design of a device to record the mentioned parameters, followed by an appropriate validation process. Should development and testing be successful, an eventual comparison in PMR with the use of continuous fetal monitoring vs current monitoring would address the hypothesis. It is suggested that a timely yet reliable indication of fetal wellbeing obtained via long-term monitoring would allow prompt and appropriate obstetric intervention and consequently reduce PMR.

Simple Analogue VLSI Circuit of a Cortical Neuron

This paper presents a novel analogue VLSI circuitry that reproduces spiking and bursting firing patterns of cortical neurons, using only 14 MOSFETs. The circuit provides a basic building block for the development of neuromorphic architectures. It enables implementation of many neurons in a single silicon chip while exhibiting flexibility in obtaining different types of adaptive and oscillatory neuron behaviours, by simply adjusting the biasing voltage. The simulation results, using a 0.35um CMOS technology, are presented.

A CMOS circuit implementation of a spiking neuron with bursting and adaptation on a biological timescale

This paper proposes a silicon neuron circuit which uses a slow-variable controlled leakage term to extend the repertoire of spiking patterns achievable in an integrate and fire model. The simulations reveal the potential of the circuit to provide a wide variety of neuron firing patterns observed in neocortex, including adapting and non-adapting, regular spiking, fast spiking, bursting, chattering, etc. The firing patterns of basic cell classes are obtained with a simple adjustment of four biasing voltages. The circuit operates in the sub-threshold regime, with time constants similar to biological neurons, and hence is suitable for use in systems requiring such operating speeds. Envisaged applications of the proposed circuit are in large-scale analogue VLSI systems for spiking neural network simulations, brain-inspired circuits for robotics and hybrid silicon/biology systems.

Maternal perception of fetal movements in late pregnancy is affected by type and duration of fetal movement

Abstract Objective: A reduction in fetal movements has been proposed to identify pregnancies at risk of stillbirth. The utility of this approach is limited by variability in maternal perception of fetal movements. We aimed to determine the proportion of fetal movements observed by ultrasound that were maternally perceived and identify factors that affected maternal perception. Method: During 30-min recordings, women (n = 21) depressed a trigger upon perception of a fetal movement, while an ultrasound operator recorded observed movements according to the fetal parts involved. Results: Women perceived between 2.4% and 81.0% (median 44.8%) of movements observed on scan. Synchronous movement of the fetal trunk and limbs was more likely to be recognized than either part in isolation (60.5% versus 37.5% and 30%, respectively). The ultrasound operator judged the fetus to be moving for a significantly greater proportion of the time than mothers (median 1.5% of total recording time versus 0.7%). There was no significant relationship between the ability to perceive fetal activity and placental site, parity, amniotic fluid index or maternal body mass index. Conclusion: Variations in maternal perception of fetal movements may affect detection of a clinically significant reduction in fetal movements for some women.

Analogue CMOS circuit implementation of a dopamine modulated synapse

This paper describes a synapse circuit that approximately implements the dynamics of the dopamine (DA) modulated synapse proposed by Izhikevich (2007). The dynamics of the model, based on ‘eligibility traces’ generated according to a spike-timing-dependent plasticity (STDP) rule, ensure that causal pre-/post- synaptic spiking activity in the time preceding the reward, signaled by DA, leads to strengthening of the synaptic connections. The circuits are designed and fabricated in a 0.35 µm CMOS technology and the simulation results are presented. This circuit block is a good candidate for the development of neuromorphic VLSI architectures that implement brain-inspired computation using biologically plausible reinforcement learning strategies.

Heterogeneous neurons and plastic synapses in a reconfigurable cortical neural network IC

This paper presents an analogue VLSI circuit intended to be used in a neural network architecture that closely resembles the small-scale laminar micro-circuits of the neocortex. The Cortical Neural Layer (CNL) chip comprises of 120 reconfigurable cortical neurons and 7,560 synapses. The neurons can be configured to produce regular spiking, fast spiking, chattering, intrinsically bursting, and other complex activity patterns. The synaptic circuits include inhibitory/ excitatory, facilitating/depressing and spike-time dependent plasticity (STDP) dynamics. The connectivity of the neural network can be configured using off-chip spike-routing and on-chip axonal arbor connections. A pre-synaptic spike can be sent to a group of crossbar synapses simultaneously, reducing latency in the pre-synaptic spike routing, enabling a high degree of connectivity of the neural network. The device is fabricated in a 0.35 μm CMOS technology and on-chip neural dynamics are experimentally verified.