Jaydeb Bhaumik

An Improved Double Byte Error Correcting Code Using Cellular Automata

Cellular Automata(CA) based VLSI implementation of t-byte errors correcting code has been established by previous research to be superior to the other existing techniques employed for realizing Reed-Solomon(RS) code. However, the scheme suffers from the limitation that it can correct ti¾?byte errors (ti¾? 2) provided errors are confined either wholly to the information bytes or entirely to the check bytes. The work reported in the present paper overcomes this limitation and corrects the errors likely in both information and check bytes. Moreover one weakness found in an earlier similar work has been identified and rectified using a modified check symbol expressions.

New Architectural Design of CA-Based Codec

Cellular automata (CA) has already established its novelty for bits and bytes error correcting codes (ECC). The current work identifies weakness and limitation of existing CA-based byte ECC and proposes an improved CA-based double byte ECC which overcomes the identified weakness. The code is very much suited from VLSI design viewpoint and requires significantly less hardware and power for decoding compared to the existing techniques employed for Reed-Solomon (RS) Codes. Also it has been shown that the CA-based scheme can easily be extended for correcting more than two byte errors.

An AES - based Robust Image Encryption Scheme

The security of digital information has become a major issue during the last three decades. Encryption is one of the ways to ensure confidentiality for the digital data. Protection of multimedia data is now becoming a big challenge to create a healthy digital world. A large number of algorithms for data and image encryption are reported in the literature. Unfortunately, all traditional cryptosystems can‟t fulfill all the requirements of image encryption. Cryptographic weakness or high computational cost does not fulfill the real time requirement for the encryption technique. In this paper a novel approach is developed to encrypt the digital image which ensures better security with optimum cost. A linear transformation is done before encrypting an image by the Advanced Encryption Standard (AES) in ECB mode. The results show that the correlation between adjacent image elements is significantly reduced by employing the proposed scheme compared to other schemes. The histogram, correlation, entropy analysis as well as differential cryptanalysis of proposed image encryption scheme have been done to justify the strength of the proposed scheme. General Terms Security, Image Encryption

Comments on “VLSI implementation of Reed-Solomon encoder algorithm for communication systems”

This comment points out the four inaccurate equations and incorrect output parity values computed using RS(255, 223) encoder algorithm. The four correct equations and correct output parity values for the given input are provided here.

Design and implementation of Cellular Automata based diffusion layer for SPN-type block cipher

In this paper, a new method to design a diffusion layer based on maximum distance separable codes for a Substitution permutation Networks (SPN)-type block cipher is proposed. The proposed diffusion layer has been designed employing the properties of maximum-length group Cellular Automata (CA). Diffusion layer of lengths 16-bit, 32-bit, 64-bit and 128-bit have been implemented using CA and combinational logic gates. Synthesis results of proposed diffusion layer on a FPGA platform are given.

Design and Implementation of RS (32, 28) Encoder and Decoder Using Cellular Automata

RS (32, 28) code is popularly used for compact disk player. In this work, a modular architecture of RS (32, 28) encoder and decoder employing the regular structure of Cellular Automata (CA) has been proposed. The work also identifies a mistake in an existing related work and recti- fies it for locating double errors. The proposed CA based double error correcting codec can be easily extended to 3, 4, 5 byte error correcting codes. CA-based VLSI design is attractive because of its simplicity, regularity and higher throughput.

Pre-layout decap allocation for power supply noise suppression and performance analysis of 512-point FFT core

This paper deals with the estimation of decoupling capacitance (decap) based on their power supply noise suppression and proper allocation of decap at the pre-layout level. By early prediction and allocation of decap at appropriate locations in the pre-layout circuit can only provide a better scope in optimizing noise, power and delay effects for the circuit. The novelty of our work lies in exhaustive estimation of power supply noise, followed by an algorithmic estimation and appropriate allocation of decap with an effort to keep noise, delay and power performance to its best. We choose 512-point FFT processor for our test circuit. To the best of our knowledge Power Distribution Network (PDN) analysis for execution time and noise suppression on FFT application cores is not available in related research works. By using our approach, power supply noise has been suppressed by 37.7%, delay and power consumption increases by 1.12% and 2.03% respectively at the pre-layout stage. This early predictions helps to create more accurate design at the layout stage and hence this work can serve as benchmark for PDN analysis.

Compact RS(32, 28) Encoder

Reed–Solomon codes are commonly used to detect and correct errors in digital data during transmission and storage. In this paper, a new optimization algorithm has been proposed which is very simple and efficient for reducing the complexity of the Galois field constant multipliers in terms of XOR2 gates, and hence, the area overhead of RS(32, 28) encoder decreases. RS(32, 28) encoder has been implemented using four optimized constant field multipliers. Using proposed algorithm, the number of XOR2 gates can be reduced by 34.95 and 50.49 %, respectively, for local and global optimization over non-optimized design without affecting its delay. The number of slices and LUT required for FPGA-based design of RS(32, 28) encoder is also reduced compared to unoptimized design.

Relative Performance Analysis of Different CMOS Full Adder Circuits

Different adder circuits are elementary blocks in many contemporary integrated circuits, which are not only employed to perform addition operations, but also other arithmetic operations such as subtraction, multiplication and division. Full adder is the basic building block of any adder circuit. Area, speed and power are the three main design metrics for any VLSI circuit. In this work, eight different full adders’ circuits based on standard (std.) CMOS, CPL, 16Transistor, DCVSL, PTL, TGA, 14-Transistor and 8Transistor have been designed and implemented using Tanner EDA simulation tool. In this paper, authors have compared the propagation delay, power consumption and power delay product (PDP) of different full adder circuits by varying supply voltage (Vdd).

TBLT-AES: A Robust Image Encryption Scheme

Abstract In the digital world, security is an important issue, and encryption is one of the ways to ensure confidentiality. Especially protection of multimedia data is now becoming a big challenge to us. A large number of algorithms for data and image encryption are reported in the literature. But due to their cryptographic weakness or high computational cost, many of them are not suitable in practical applications. In this paper, we introduce an image encryption scheme where a linear transformation is performed before encryption. The encryption is done by employing Advanced Encryption Standard (AES) in Electronic Code Book mode to achieve high throughput. The results showed that the correlation between adjacent image elements was significantly reduced by employing the proposed scheme compared to other schemes. The histogram, correlation, entropy analysis as well as differential cryptanalysis have been done to justify the strength of the proposed scheme.