Dipanwita Roy Chowdhury

Progress in Cryptology - INDOCRYPT 2008

Stream Ciphers.- Slid Pairs in Salsa20 and Trivium.- New Directions in Cryptanalysis of Self-Synchronizing Stream Ciphers.- Analysis of RC4 and Proposal of Additional Layers for Better Security Margin.- New Results on the Key Scheduling Algorithm of RC4.- Cryptographic Hash Functions.- Two Attacks on RadioGatun.- Faster Multicollisions.- A New Type of 2-Block Collisions in MD5.- New Collision Attacks against Up to 24-Step SHA-2.- Public-Key Cryptography - I.- Secure Hierarchical Identity Based Encryption Scheme in the Standard Model.- A Fuzzy ID-Based Encryption Efficient When Error Rate Is Low.- Type-Based Proxy Re-encryption and Its Construction.- Toward a Generic Construction of Universally Convertible Undeniable Signatures from Pairing-Based Signatures.- Security Protocols.- Concrete Security for Entity Recognition: The Jane Doe Protocol.- Efficient and Strongly Secure Password-Based Server Aided Key Exchange (Extended Abstract).- Round Efficient Unconditionally Secure Multiparty Computation Protocol.- A New Anonymous Password-Based Authenticated Key Exchange Protocol.- Group Key Management: From a Non-hierarchical to a Hierarchical Structure.- Hardware Attacks.- Scan Based Side Channel Attacks on Stream Ciphers and Their Counter-Measures.- Floating Fault Analysis of Trivium.- Algebraic Methods in Side-Channel Collision Attacks and Practical Collision Detection.- Block Ciphers.- New Related-Key Boomerang Attacks on AES.- New Impossible Differential Attacks on AES.- Reflection Cryptanalysis of Some Ciphers.- A Differential-Linear Attack on 12-Round Serpent.- New AES Software Speed Records.- Public-Key Cryptography - II.- A New Class of Weak Encryption Exponents in RSA.- Two New Efficient CCA-Secure Online Ciphers: MHCBC and MCBC.- Cryptographic Hardware.- Chai-Tea, Cryptographic Hardware Implementations of xTEA.- High Speed Compact Elliptic Curve Cryptoprocessor for FPGA Platforms.- Elliptic Curve Cryptography.- More Discriminants with the Brezing-Weng Method.- Another Approach to Pairing Computation in Edwards Coordinates.- Threshold Cryptography.- A Verifiable Secret Sharing Scheme Based on the Chinese Remainder Theorem.- Secure Threshold Multi Authority Attribute Based Encryption without a Central Authority.

Secured Flipped Scan-Chain Model for Crypto-Architecture

Scan chains are exploited to develop attacks on cryptographic hardware and steal intellectual properties from the chip. This paper proposes a secured strategy to test designs by inserting a certain number of inverters between randomly selected scan cells. The security of the scheme has been analyzed. Two detailed case studies of RC4 stream cipher and AES block cipher have been presented to show that the proposed strategy prevents existing scan-based attacks in the literature. The elegance of the scheme lies in its less hardware overhead.

Design of CAECC - cellular automata based error correcting code

A new scheme for designing error detecting and error correcting codes around cellular automata (CA) is reported. A simple and efficient scheme for generating SEC-DED codes is presented which can also be extended for generating codes with higher distances. A CA-based hardware scheme for very fast decoding (and correcting) of the codewords is also reported. >

CA-based byte error-correcting code

This paper reports a novel approach for designing byte error-correcting codes using cellular automata (CA). A simple scheme for generation and decoding of single-byte error-correcting and double-byte error-detecting codes, referred to as CA-SbEC-DbED, is presented. Extension of the scheme to locate/correct larger number of information byte errors has been also included. The encoding and decoding algorithms have been designed with the help of a linear operator that can be conveniently realized with a maximum length group CA. The regular, modular and cascadable structure of CA can be economically built with VLSI technology. Compared to the existing architecture of the Reed-Solomon decoder chip, CA-based implementation of the proposed decoding scheme provides a simple cost effective solution. >

Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks

All elliptic curve cryptographic schemes are based on scalar multiplication of points, and hence its faster computation signifies faster operation. This paper proposes two different parallelization techniques to speedup the GF(p) elliptic curve multiplication in affine coordinates and the corresponding architectures. The proposed implementations are capable of resisting different side channel attacks based on time and power analysis. The 160, 192, 224 and 256 bits implementations of both the architectures have been synthesized and simulated for both FPGA and 0.13@m CMOS ASIC. The final designs have been prototyped on a Xilinx Virtex-4 xc4vlx200-12ff1513 FPGA board and performance analyzes carried out. The experimental result and performance comparison show better throughput of the proposed implementations as compared to existing reported architectures.

Fault analysis of grain-128 by targeting NFSR

Fault attack is one of the most efficient form of side channel attack against implementations of cryptographic algorithms. This kind of attacks have been shown to be extremely successful against stream ciphers. The eStream cipher Grain-128 has already been shown to be weak against fault attack, when faults are injected in the LFSR. In this paper, we show that Grain-128 can also be attacked by inducing faults in the NFSR. The attack requires about 56 fault injections for NFSR and a computational complexity of about 221.

Cellular Automata—Theory and Applications

Advances in microelectronics have made possible design of a wide variety of innovative structures with Very Large Scale Integrated (VLSI) circuits, However, design of complex VLSI circuits within reasonable cost demands two essential pre-requisites—‘regularity’ and ‘simplicity’. These two qualities are inherent to the Cellular Automata (CA) structure. A large variety of physical systems have been simulated using this structure. A survey of all such major developments have been reported in the present paper. It highlights a wide variety of applications which can be tackled by the CA hardware built around VLSI technology. After surveying general CA structure, the paper concentrates on the theory and applications of additive cellular automata as a built-in-self-test structure within a VLSI chip.

An Efficient Approach to Develop Secure Scan Tree for Crypto-Hardware

Scan chain based test has been a common and useful method for testing VLSI designs due to its high controllability and observability. However scan chains have recently been shown to pose security threat to cryptographic chips. Researchers have proposed various prevention architectures like scan tree followed by a compactor, locking and TAP architecture. But these solutions lead to huge hardware overhead and slow the process of testing. In this paper we propose a novel secured scan tree architecture which has very low gate overhead, high fault coverage and is amenable to fast online testing.

A low-cost high-capacity associative memory design using cellular automata

The present paper reports a novel scheme for designing fast retrieval memory system using cellular automata. In essence, the proposed scheme implements the concept of hashing in hardware. This makes possible the design of low-cost high-capacity memory systems with limited content addressability as an option. The efficiency of the scheme has been verified through extensive simulation studies of the hardwired hashing function built around 1D and 2D linear cellular automata (CA). >

Cellular automata based synthesis of easily and fully testable FSMs

The paper reports an application of a special class of non-group cellular automata, referred to as D1/sup */CA, as the test machine embedded in the FSM to be synthesized. The state transition properties of D1/sup */CA are exploited in designing an easy testing scheme for the finite state machine. The scheme has been found to incur a small area overhead while providing extremely high coverages close to 100% for all single stuck-at faults in the circuit.