Je-Gwang Yoo

Package-on-Package (PoP) for Advanced PCB Manufacturing Process

In the 1990s, both BGA (ball grid array) and CSP (chip size package) are entering their end in the front-end packaging materials and process technology. Both BGA and CSP like SMD (surface mount device) from the 1980s and THD (through-hole mount device) from the 1970s are reaching its own impasse in terms of maximizing its electrical, mechanical, and thermal performances, size, weight, and reliability. Now, 3D packages are the next phase for its future use in advanced PCB manufacturing process. They can be classified into wafer level, chip level, and package level stacking. So, package-on-package (PoP), a type of 3D package level stacking, is to be discussed in this paper (Kada et al.)

Comparison Study from Sputtering, Sol-Gel, and ALD Processes Developing Embedded Thin Film Capacitors

Three methods for fabricating thin film capacitors are investigated using sputtering, sol-gel, and atomic layer deposition (ALD) techniques for advanced packaging applications for embedded capacitors. In particular, the microstructures and the electrical properties of ceramic oxide films Au/Ti/Al₂O₃ for ALD are being studied while ferroelectric thin films Au/Ti/BaTiO₃ for sol-gel and Cu/Ba_1-XSr_XTiO₃ for sputtering are being discussed in detail. The upper Au/Ti electrode layer is deposited by dc magnetron sputtering on top of Al₂O ₃ (ALD process) and on BT layer to complete the Au/Ti/BaTiO ₃/Ni/Cu/FR4/Cu (sol-gel process) structure respectively whereas Cu is deposited by sputtering on top of the BST layer to complete the Cu/Ba_1-XSr_XTiO₃/Cu/SiO₂/Si (sputtering process). After a careful comparison is done, ALD for the Al ₂O₃ thin film seems to show the most promising process for its low temperature at 150degC and for its electrical properties like a capacitance of 0.88nF/mm² with less then plusmn2% tolerances, a dissipation factor of less than 0.018, and a low leakage current less than 0.1muA/cm² at 4 V