Ioan Sauciuc

Spreading in the heat sink base: phase change systems or solid metals??

Presently, the microelectronics industry needs thermal solutions that are able to dissipate high heat fluxes at low thermal resistance. The majority of original equipment manufacturers (OEMs) within the microelectronics industry would like to achieve this by extending the application of air-cooling technologies since it implies minimal impact to the design of computer systems and is known to be a cost effective solution space. Spreading resistance through the base of the heat sink is one major component of the total thermal resistance from the silicon junction to the local ambient, especially if larger volume heat sinks are to be used. Until now, most of the research has focused on using phase change systems (i.e., vapor chambers) for reducing the spreading resistance of the heat sink base. Since no significant improvements have been achieved, there is a need to determine the envelope of the limitations for phase change-heat spreaders used in processor cooling, and to compare their performance against high thermal conductivity solid metals. Two simple models are presented to address the heat transfer limitations in phase change systems. Using these models, the ratio of phase change spreading resistance over solid metal spreading can be estimated.

THERMAL PERFORMANCE AND KEY CHALLENGES FOR FUTURE CPU COOLING TECHNOLOGIES

Over the past few years, thermal design for cooling microprocessors has become increasingly challenging mainly because of an increase in both average power density and local power density, commonly referred to as “hot spots”. The current air cooling technologies present diminishing returns, thus it is strategically important for the microelectronics industry to establish the research and development focus for future non air-cooling technologies. This paper presents the thermal performance capability for enabling and package based cooling technologies using a range of “reasonable” boundary conditions. In the enabling area a few key main building blocks are considered: air cooling, high conductivity materials, liquid cooling (single and two-phase), thermoelectric modules integrated with heat pipes/vapor chambers, refrigeration based devices and the thermal interface materials performance. For package based technologies we present only the microchannel building block (cold plate in contact with the back-side of the die). It will be shown that as the hot spot density factor increases, package based cooling technologies should be considered for more significant cooling improvements. In addition to thermal performance, a summary of the key technical challenges are presented in the paper. This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.Copyright

Use of heat pipe/heat sink for thermal management of high performance CPUs

This paper will describe various cooling solutions in notebook PC and desktop/server applications. In the notebook PC application, miniature heat pipes of diameter 3-6 mm, flatten to desire thickness, are commonly used to improve heat spreading and more efficient transfer heat generated from the CPU to a remote heat dissipation area. Examples of three typical thermal solutions in notebook PC are given in this paper. Whereas in the desktop server application, flat type rectangular heat pipes or so-called vapor chambers are used to attach under the base of the heat sink to help temperature uniformity across the heat sink base. This will reduce the spreading resistance in the heat sink base and therefore improve the heat sink performance. Experimental results showed that with a vapor chamber installed can achieved a 45% improvement in the heat sink performance for heat sink of length 110 mm, width 72.5 mm, height 50 mm and base thickness 7 mm.

Key challenges for the piezo technology with applications to low form factor thermal solutions

The thermal performance of piezoelectric actuators for cooling in low form factor applications is presented. A significant reduction in thermal resistance is achievable when compared to the baseline natural convection. Comparisons with fans and blowers of similar size result in comparable performance but at greatly reduced power consumption

Thermal Devices Integrated With Thermoelectric Modules With Applications to CPU Cooling

Over the past few years, the air cooling technology improvements present diminishing returns for microprocessors cooling applications. Presently most of the proposed future cooling technologies (i.e. pumped liquid cooling or vapor compressor refrigeration) may need some fluid moving device and a large remote heat exchanger which requires additional volume. Due to the complexity, reliability issues and space requirements it is preferred to extend the air cooling within the current form factors and using passive devices. This paper will show that optimized thermoelectric modules combined with two-phase (liquid/vapor) passive devices can further improve the cooling capability compared to conventional air cooling technologies at reasonable thermoelectric cooler (TEC) power consumption. Current computational fluid dynamics programs are not yet well equipped to find out the most optimized TEC geometry (for a given COP and given thermal requirements) in a reasonable amount of computation time. Therefore, two modeling steps are proposed: find out the preliminary TEC geometry using an ID analytical program (based on uniform heat flux and a given COP) and use it as an input to CFD programs (i.e. Icepak®) for detailed predictions. Using this model, we confirmed that the conventional TEC technology must use some spreading device to dissipate the CPU heat to the TEC cold side. Different spreading devices are considered: solid metal, heat pipe, vapor chambers and single/two phase pumped cooling. Their individual performance integrated with TEC will be presented. In addition, we propose that the TEC performance to be controlled as a function of instantaneous CPU power consumption, ambient temperature and other parameters. This controller offers extra flexibility which can be used for either noise reduction or TEC power reduction. However, such power cycling of the TEC may affect the TEC reliability. Power cycling accelerated test data (>500,000 accelerated cycles) have been performed together with the life predictions will be presented in the paper.Copyright

The design and testing of the super fiber heat pipes for electronics cooling applications

Cooling of electronics is one of the major fields of application for heat pipes (3-9-mm outside diameter) with a worldwide demand exceeding one million per month. The high heat fluxes associated with electronics cooling require heat pipes with high maximum heat transfer at any inclination, and therefore improved wick structures are needed. In particular, the operation at top heat mode (vertical orientation) is required by most notebook manufacturers with a decrease of 30%-50% of the thermal resistance over conventional systems. A new wick structure has been developed so the capillary channels are increased with small effects on the heat pipe permeability. Using this new design criterion, (which balances the permeability and capillary needs), super fiber bundle heat pipes have been developed. The diameter of the wire used in the fabrication varied from 0.05 to 0.1 mm and the maximum input power was 16 W. It was found that the vapor space/liquid space ratio is an important parameter for this type of heat pipe. The test results show that the thermal resistance of the heat pipes is a strong function of the orientation. We have fabricated heat pipes with two to five times lower thermal resistance than previous conventional heat pipes (for the top heat mode operation). A comparison with other types of wick structures is also presented. Thermal resistances as low as 0.5/spl deg/C/W (top heat mode) and 0.2/spl deg/C/W (horizontal operation) have been observed. The application to electronics cooling it has been successful, especially in notebook computers and telecommunications applications.

Piezoelectric Actuators for Low-Form-Factor Electronics Cooling

The cooling performance of piezoelectric actuators is evaluated for low-form-factor electronics in this work. A piezoelectric actuator is a cantilever made from metal or plastic with a piezoelectric material bonded to it. Under an alternating electrical current, the piezo actuator oscillates back and forth, generating airflow. Compared to conventional fans, these actuators have the advantages of low power consumption, low noise, and smaller dimensions. The parameters investigated in the experiments are actuator orientation, actuator-to-heat source distance, and actuator amplitude. For an actuator power consumption of 31 mW, the heat source temperature was lowered by more than 25°C compared to natural convection conditions (for a 2.45 W heater power dissipation). Performance comparisons against axial fans and natural convection heat sinks show that the piezo actuators perform significantly better in terms of power consumption and cooling volume. This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.Copyright

Time-ordered events CPU reliability assessment

IC product use conditions (UCs) are needed to enable accurate reliability modeling in the context of knowledge-based qualification. We describe a method of use condition development which is based on the sequence of user foreground events from field surveys. Events are converted to temperature and voltage use condition traces accounting for lab data on representative workloads and thermal modeling. The temperature and voltage data are paired for client CPU UC data and used to estimate the reliability risks for both silicon and thermo-mechanical failure mechanisms. The new approach are validated using field consumer data. We also describe the future work needed on how to account for concurrent events and the implications on TOE methodology.

Carbon based Thermal Interface Material for high performance cooling applications

Currently, a variety of Thermal Interface Materials (TIMs) are required to meet specific requirements for various products with no single TIM meeting the needs for all CPU market segments. Surface treatments, reflow temperatures, mechanical load, performance targets all play a role in choosing a specific TIM. Based on the above multitude of conditions, it is desirable to find a universal TIM that would enable all the products across all markets. To meet these requirements and based on legacy data, efforts should focus on TIMs that (1) have high bulk conductivity (i.e. > 20 W/mK) and (2) do not have hard or brittle contact surfaces and 3) are reliable over the years of normal usage. The focus of this paper is on a novel material called Vertical Carbon TIM (VCTIM). This composite TIM consists of a soft polymer matrix and carbon flakes aligned in the z-direction (i.e. the direction of the heat flow in the semiconductor package). Previous efforts of graphite/graphene and different matrix material were tried by academia and industry [1]-[5], but this TIM, is one of the first non-metal solid TIMs to achieve high z-bulk thermal conductivity (i.e. > 30 W/mK) and low contact resistance in the TIM tester [6]. These fundamental thermal properties are showing promise in meeting the requirements listed above. The first part of the paper will focus on presenting the fundamental thermal/mechanical material properties which have a significant effect on overall package thermal performance. Through separating the bulk thermal resistance from the contact resistance, we are better able to explain the degradation of VCTIM thermal performance in a package. The empirical data gained through this characterization is then compared to a published physics based model of thermal contact resistance [6], [7]. The model predicts a contact resistance that scales with contact area which in turn is a function of surface height variation (or roughness), hardness, and pressure. The interfacial thermal contact resistance of VCTIM is found to fit well with this model. Additionally, it is found that changes in thermal performance of VCTIM upon exposure to reliability conditions can be explained within the context of this model. The second part will show thermal data which include the effect of different reliability stresses, including bake, temperature and humidity exposure, and temperature cycling. The fundamental explanation of this behavior, which relates the material properties to the mechanical boundary conditions, will be included with the focus on delamination at the interface and increased hardness during bake or temperature and humidity exposure. Contrary to polymeric TIMs, [9] it will be shown that VCTIM has small thermal degradation through thermal degradation in bake at 125°C. We will also show the effect of matrix material composition changes on significantly eliminating degradation through temperature and humidity exposure (highly accelerated stress testing (HAST) 110°C/85% relative humidity). Other factors examined in the paper include VCTIM thickness, die thickness, and IHS thickness. Also it will be shown that increasing TIM thickness improves reliability and compressibility performance. The material challenges like limited compressibility and the plastic behavior will also be discussed. The final paper section will provide TIM2 package build evaluation data.

Package induced stress impact on transistor performance for ultra-thin SoC

Integrated Circuits continuously scale including die thicknesses to achieve lower total z-height. As has been previously reported, die thinning can impact transistor performance due to mechanical stresses generated by the package. This paper is investigating the impact on the tri-gate transistors performance for die thickness below 100μm through BGA solder board attach. Ring oscillators are used to assess transistor performance with frequency data collected at wafer level, packaged unit, and board mounted levels. PMOS and NMOS effects are extracted independently using appropriately weighted oscillators. Results show that PMOS drive current increases while NMOS drive current decreases with reductions in die thickness, consistent with FEA modeling. The impact of die over-mold thickness on the transistor saturation current shifts is also included and demonstrates the importance of considering such factors in establishing the correct balance between transistor performance impact and other characteristics such as package warpage.