Jean-Luc Autran

Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from a Ta(OC2H5)5 precursor

In this work, the structural and electrical properties of amorphous and crystalline Ta2O5 thin films deposited on p-type Si substrates by low-pressure chemical vapor deposition from a Ta(OC2H5)5 precursor have been investigated. The as-deposited layers are amorphous, whereas crystalline Ta2O5 was obtained after postdeposition O2 treatment at 800 °C. As evidenced by x-ray diffraction, a hexagonal structure was obtained in the latter case. Physicochemical analysis of our layers shows that the O2-annealing step leads to the growth of a thin (∼1 nm) interfacial SiO2 layer but was not sufficient to reduce the level of hydrocarbon contamination. The dominant conduction mechanism in amorphous Ta2O5 is clearly due to the Poole–Frenkel effect, whereas the situation remains unclear for crystalline Ta2O5 for which no simple law can be invoked to correctly describe its conduction properties. From capacitance–voltage measurements, the dielectric constant was found to be ∼25 for amorphous samples, but values ranging fr...

75 nm damascene metal gate and high-k integration for advanced CMOS devices

An advanced CMOS process has been proposed which include key features: 75 nm gate length damascene metal gate, high-k dielectrics with 1.35 nm EOT. Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface. Low Ioff and low gate current make the technology attractive for low standby power applications.

On the tunneling component of charge pumping current in ultrathin gate oxide MOSFETs

A simple method is described for separating the charge pumping current from the parasitic tunneling component in a charge pumping measurement performed on MOS transistors with ultrathin (<2 nm) gate oxide thickness. The method is presented here for a two-level charge pumping signal and can be used to significantly increase the accuracy of the technique to extract interface trap parameters in tunnel MOS devices.

Frequency characterization and modeling of interface traps in HfSixOy/HfO2 gate dielectric stack from a capacitance point-of-view

A time-resolved analysis of the capacitance–voltage (C–V) technique and an inverse modeling approach have been developed to determine the energy distribution and the capture cross section of interface traps in the silicon band gap from multifrequency C–V measurements. In this work, our method is performed on n-type metal-oxide-semiconductor capacitors with HfSixOy/HfO2 gate dielectric stack and polysilicon gate. From the frequency dispersion of C–V data, we evidence a peak of acceptor states in the upper half of the band gap at 0.81 eV above the valence band and characterized by a capture cross section of 1.5×10−17 cm2. This value is approximately ten times lower than typical capture cross sections relative to the dangling bonds (Pb centers) at the Si/SiO2 interface, which is in good agreement with a Coulombic center model predicting a capture cross section inversely proportional to the square of the dielectric permittivity.

Fabrication and characterization of Si-MOSFET's with PECVD amorphous Ta 2 O 5 gate insulator

Silicon MOS transistors having amorphous Ta/sub 2/O/sub 5/ insulator gates have been fabricated. The Ta/sub 2/O/sub 5/ films were deposited using a low pressure (a few mtorr) plasma-enhanced CVD process in a microwave (2.45 GHz) excited electron cyclotron resonance reactor. The source gas was TaF/sub 5/. Electrical characteristics of p-channel Al gate transistors are presented.

Electrical properties of Ta2O5 films obtained by plasma enhanced chemical vapor deposition using a TaF5 source

High quality Ta2O5 thin films have been obtained from TaF5 and O2 using a microwave excited electron cyclotron resonance plasma at low pressure (∼2 mTorr). Physical and electrical measurements reveal that the as‐deposited amorphous films have excellent properties: refractive indices ∼2.16, dielectric constants ∼25, and leakage currents <10−10 A cm−2 at 2.5 V (0.3 MV cm−1, 85 nm thick, 13 nm SiO2 equivalent). Trapping and conduction properties of these layers have also been investigated, showing a reversible electron trapping and a trap‐limited Poole–Frenkel effect.

CONDUCTION MECHANISMS IN TA2O5/SIO2 AND TA2O5/SI3N4 STACKED STRUCTURES ON SI

In this paper, the conduction mechanisms in Ta2O5/SiO2 and Ta2O5/Si3N4 stacked structures on Si are investigated both experimentally and theoretically. Amorphous Ta2O5 films (20–60 nm thick) were deposited by low pressure chemical vapor deposition or electron cyclotron resonance plasma enhanced chemical vapor deposition and some layers were annealed for crystallization at 800 °C in O2. The Si3N4 layers were formed by plasma nitruration or low pressure chemical vapor deposition. The SiO2 films studied were intentionally obtained by dry oxidation of the Si substrates, or as a result of the Ta2O5 deposition process (due to the oxidizing atmosphere), or of the Ta2O5 postdeposition annealing treatment under O2. The conduction mechanisms were identified by comparing the experimental current–voltage traces to the theoretical curves calculated in steady-state regime by using the Kirchhoff voltage law and the current continuity equation. In amorphous Ta2O5, the conduction mechanisms identified are the electronic h...

Altitude and Underground Real-Time SER Characterization of CMOS 65 nm SRAM

We report real-time SER characterization of CMOS 65 nm SRAM memories in both altitude and underground environments. Neutron and alpha-particle SERs are compared with data obtained from accelerated tests and values previously measured for CMOS 130 nm technology.

Heavy Ion Testing and 3-D Simulations of Multiple Cell Upset in 65 nm Standard SRAMs

Heavy ions experiments are carried out on commercial 90 nm and 65 nm SRAMs. The contribution of single and multiple cell upsets (MCUs) are discussed as a function of the LET for different memory cell areas and for triple well usage. Once again, well engineering plays a key role on MCU and SEE response of SRAM. Full 3-D TCAD simulations investigate the occurrence of parasitic bipolar effect.

Technology downscaling worsening radiation effects in bulk: SOI to the rescue

Atmospheric radiation is today as important to IC reliability as intrinsic failure modes. In non-critical consumer applications (cell phone, printer, gaming), a relatively high soft error rate (SER) is often tolerable. In contrast, a similar failure rate would be deemed unacceptably high in an arena where system reliability, accessibility, and serviceability are of paramount importance (networking, server, avionic, space), particularly where human life or safety is at risk (medical, automotive, transportation). Increasing number of industry segments are impacted due to growing amount of memory and logic components per circuit. Concurrently, sub-45nm downscaling has a profound impact on SER of bulk CMOS technologies. The enhanced resilience of latest SOI technologies helps to leverage existing robust design solutions. In this paper, experimental radiation test results and simulations are reported for the first time in UTBB FDSOI 28nm and compared to Bulk, PDSOI and FinFET alternatives.