Gilles Gasiot

Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering

Neutron and alpha SER test results are presented for two SRAMs processed in a commercial 65 nm CMOS technology. Devices with the commonly used triple well option have higher rates of multiple cell upsets (MCU) and therefore higher SER. The same behavior is reported for older technologies from 180 nm to 65 nm. Full 3-D device simulations on 65 nm SRAM cells quantify the amplification of the charge collection with the usage of triple well and frequency of well contacts.

Impacts of front-end and middle-end process modifications on terrestrial soft error rate

This paper reviews soft error rate (SER) mitigations with standard process modifications in up-to-date commercial CMOS SRAMs and flip-flops. Acting in the front-end or middle-end levels, the following technology options are mainly evaluated: well engineering, partially and fully depleted silicon-on-insulator (FD SOI), and MIM capacitors. SER robustness gains are compared for eight classical process options based on original and published data. The best hardening efficiencies for SRAMs arise from the addition of stacked capacitors and the use of partially depleted (PD) SOI. SER trends are also reported for FD SOI and dual gates.

Comparisons of soft error rate for SRAMs in commercial SOI and bulk below the 130-nm technology node

This paper presents experimental ASER on SOI and BULK SRAMs for the 250-, 130-, and 90-nm technologies. The key parameters controlling soft error rate (SER) in these technologies are modeled with Monte Carlo simulations to predict SER to the 65-nm node.

Insights on the transient response of fully and partially depleted SOI technologies under heavy-ion and dose-rate irradiations

The sensitivity of SOI technologies to transient irradiations (both dose rate and heavy ions) is analyzed as a function of the technology architecture with experiments and simulations. Two main parameters are considered. First, the thickness of the silicon film, which determines the fully or partially depleted state of SOI devices. This parameter strongly influences the parasitic bipolar, which amplifies the radiation-generated charge. In particular, fully depleted devices show a low bipolar gain due to a high-impact ionization. Secondly, the doping profile in the drain region, which varies with process optimization. The trend is to use shallow junctions to reduce short-channel effects in partially depleted devices. Shallow-drain junctions in partially depleted devices contribute to increases in drain-region sensitivity. As a result, fully depleted architectures are more adapted to reduce the radiation sensitivity of future SOI technologies, because it both reduces the bipolar amplification and the sensitivity of the drain region.

A Comprehensive Study on the Soft-Error Rate of Flip-Flops From 90-nm Production Libraries

This paper presents a study using alpha- and neutron-accelerated tests to characterize the soft error rate (SER) of flip-flops (FFs) that are used in 90-nm CMOS production designs. The investigated FFs differ in circuit schematic, threshold voltage (VT), drive strength, and cell height. Both the alpha- and the neutron-induced SER of FFs on a dedicated 90-nm test chip showed a strong dependence on clock and data state. Theoretical results demonstrate that the FF SER is modeled best if particle hits at both the NMOS and the PMOS drains are included and if the resulting current pulse is assumed to have a width of approximately 5 ps. Furthermore, the impact of process variations on the FF SER is shown to depend strongly on the data state and on the applied pulsewidth. On average, the SER per bit of the investigated FFs is higher than the typical SER per bit of unprotected static random access memories in 90 nm and has increased with a factor of 3 per technology generation. The reported results illustrate the importance of the characterization of FF SER in order to design reliable integrated circuits.

Criterion for SEU occurrence in SRAM deduced from circuit and device Simulations in case of neutron-induced SER

A reliable criterion for SEU occurrence simulation is presented. It expresses the relationship existing at threshold between the magnitude and duration of the ion-induced parasitic pulse. This criterion can be obtained by both three-dimensional device and SPICE simulations. Using this criterion, the simulated and experimental SER on 130 and 250 nm technologies are shown to be in good agreement.

Altitude and Underground Real-Time SER Characterization of CMOS 65 nm SRAM

We report real-time SER characterization of CMOS 65 nm SRAM memories in both altitude and underground environments. Neutron and alpha-particle SERs are compared with data obtained from accelerated tests and values previously measured for CMOS 130 nm technology.

Alpha-Induced Multiple Cell Upsets in Standard and Radiation Hardened SRAMs Manufactured in a 65 nm CMOS Technology

Accelerated alpha-soft error rate (SER) measurements are carried out on regular and radiation-hardened SRAMs in a 65 nm CMOS technology. Results are first compared to previous experimental radiation data in 130 nm and 90 nm. Second, the SER increase measured in 65 nm is investigated through (i) multiple cell upsets (MCU) counting and classification from experimental bitmap errors and (ii) full 3-D device simulations on SRAM bitcells to assess the PMOS-off sensitivity and the NMOS SEU threshold LET (LETth) of each tested technologies. Finally, process changes are also scanned to shed light on the 65 nm SRAM response to alpha particles

Heavy Ion Testing and 3-D Simulations of Multiple Cell Upset in 65 nm Standard SRAMs

Heavy ions experiments are carried out on commercial 90 nm and 65 nm SRAMs. The contribution of single and multiple cell upsets (MCUs) are discussed as a function of the LET for different memory cell areas and for triple well usage. Once again, well engineering plays a key role on MCU and SEE response of SRAM. Full 3-D TCAD simulations investigate the occurrence of parasitic bipolar effect.

Multiple-Bit Upset Analysis in 90 nm SRAMs: Heavy Ions Testing and 3D Simulations

SEU and MBU cross-sections are measured with heavy ions for commercial 90 nm single port and dual port SRAMs. SEU and MBU rates are discussed as a function of the LET and beam tilt. A new sensitive area devoted to MBU is computed with full 3D TCAD simulations on single and adjacent memory cells.