Jean-Luc Diot

Comprehensive design analysis of QFN and PowerQFN packages for enhanced board level solder joint reliability

Board level solder joint reliability is a critical issue for Quad Flat Non-lead Package (QFN), a type of leadframe CSP, during the thermal cycling test. However, currently there are very few papers available on fatigue modeling and thermal cycling test of QFN on board. In this paper, a parametric 3D FEA sliced model is built for QFN (4/spl times/4, 5/spl times/5, 6/spl times/6, 7/spl times/7, and 8/spl times/8) and PowerQFN-8/spl times/8 on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. It has the capability to predict the fatigue life of solder joint during the thermal cycling test. The fatigue model applied is based on Darveauxs approach with non-linear viscoplastic analysis of solder joints. The solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. Higher SED leads to shorter fatigue life. For the test vehicles studied, the maximum SED is observed mostly at the top corner of peripheral solder joint.

New package for CMOS sensors

Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.