Jean-Michel Hartmann

Bonded planar double-metal-gate NMOS transistors down to 10 nm

Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.

1.3 µm Room Temperature Emission from InAs/GaAs Self-Assembled Quantum Dots

We have investigated the growth conditions necessary to achieve strong room temperature emission at 1.3 µm for InAs/GaAs self-assembled quantum dots (QDs) using conventional solid source molecular beam epitaxy (MBE). A relatively high substrate temperature and very low growth rate (LGR) result in long wavelength emission with a small linewidth of only 24 meV. Atomic Force Micrographs obtained from uncapped samples reveal several differences between the LGRQDs and those grown at higher growth rates. The former are larger, more uniform in size and their density is lower by a factor of about 4. LGRQDs have been incorporated in p-i-n structures and strong room temperature electroluminescence detected. The light output of the QD p-i-n diodes is found to be significantly higher than a quantum well (QW) sample at least for current densities up to 0.5 kAcm-2.

Challenges and Progress in Germanium-on-Insulator Materials and Device Development towards ULSI Integration

SOITEC, Parc Technologique des Fontaines, F38190, Bernin, France The recent progress in the fabrication of GeOI substrates and devices is reviewed. Improvements have been made in threading dislocation density, Ge-buried oxide interface passivation, device performance. The potential of various co-integration schemes (lateral and vertical) has been illustrated as alternatives to the fabrication of n-type germanium channel devices. GeOI is also shown to be a versatile platform for the monolithic integration of Si and III-V devices and tunneling field effect transistors.

Temperature, density, and perturber dependences of absorption of the 3.39 µm He-Ne laser by methane

We present an experimental and theoretical study of the absorption of the IR He–Ne laser (3.39 µm) by Ch4. Shocktube measurements were made for mixture of CH4 with Ar, N2, and O2 in wide density and temperature ranges. Calculations were made by using the available spectroscopic data on CH4 absorption lines. Comparison between experiments and calculations show that the theoretical predictions are accurate for all densities up to the temperature of 1200 K. At 2000 K, the calculations fail, probably due to insufficient knowledge of hot-band lines. Furthermore, the present study shows that mixture of CH4 with Ar, O2, and N2 lead to absorptions which are similar (within experimental error), as is confirmed by the theoretical model.

Silicon Technologies for Nanoscale Device Packaging

We present our recent developments on silicon technologies dedicated to the packaging of nano-objects/nano-devices. These technologies aim at both protecting and electrically connecting a nanoscale device positioned on a perfect Si(001)-(2 × 1):H surface smoothed thanks to a 950 °C thermal treatment. The nano-device is connected to nanopads implanted on the silicon surface. Each nanopad is linked to a nanovia which is locally achieved by etching and filling processes operated in a FIB (Focused Ion Beam) equipment. Impacts of the FIB process on via morphology and properties are depicted. Nanopads are fabricated through the local implantation of arsenic, and the effect of the surface smoothing thermal treatment on the dopants diffusion length is estimated by simulation and then experimentally explored. Key process steps such as the etching of a deep cavity and the surface protection with a temporary cap are also described, and a first assembly consisting in a substrate equipped with nanopads and directly bonded with a cap substrate is presented.

Lasing in Ge1-xSnx-based photonic crystals (Conference Presentation)

The Silicon (Si) CMOS technology has long been the backbone of electronic devices. In these components, data communication is currently limited by the metal interconnects. An alternative solution based on optical transmission demands an additional light source due to the intrinsic indirect gap of Si, which prevents it from efficiently emitting light.nnThe requirement of a monolithic, Si-compatible light source has made another column IV semiconductor – Germanium (Ge) - a potential candidate. Ge has, as Si, an indirect gap, but with a smaller separation between Γ and L energy levels. A direct gap Ge-based material can be obtained by alloying it with Tin (Sn) – a column IV semi-metal. Recent studies have demonstrated lasing in optical cavities made with Ge1-xSnx alloy: So far, lasing in Fabry-Perot cavity [1, 2] and in micro-disk cavity [3, 4] were reported.nnIn this article, we study lasing in Ge1-xSnx - based photonic crystals, with 16% Sn concentration. Studies were conducted on Hn defect cavities (with n denoting the number of hexagonal ring of air holes removed from the center), and slow mode membranes – which are photonic crystals with low group velocity optical mode appeared in the photonic band structure, thus enhancing the interaction between emitted light and the gain medium.nnA step-graded epitaxy technique was used to fabricate the samples. It consists in inserting a thick buffer with discrete Sn content increases between the Ge virtual substrate underneath and the main Ge0.84Sn0.16 layer on top. With this method, misfit dislocations are distributed more evenly in the grading (instead of propagating towards the surface), which preserves the crystalline quality of the partly relaxed Ge0.84Sn0.16 optical layer. Both Hn cavities and slow mode membranes were under-etched to make the active layer fully relaxed. The photonic crystals are slightly curved due to strong relaxation of the active layer. The structures were optically pumped with a 1064 nm pulsed laser. Fourier transform infrared (FTIR) spectroscopy was used to study the photoluminescence of these samples.nnWe demonstrate lasing on the H4 cavities and the slow mode membranes. The dimensions of both structures were calculated to pin the resonance mode (or slow mode under the light cone) around the emitted wavelength of relaxed Ge0.84Sn0.16. Based on the spectra and the Lin-Lout curve, we estimate the current lowest lasing threshold around 180 kW/cm2 for slow mode membrane at low temperature (15K), with emitted wavelength of 2880 nm. The lasing threshold obtained here is of the same order of magnitude of those reported for micro-disk and Fabry-Perot cavities [1, 2, 3, 4], suggesting that the intrinsic properties of Ge1-xSnx are the main limit factor to the performance. Surface passivation and carrier confinement with SiGeSn alloys and/or multi quantum well structures should be used to enhance the Ge1-xSnx radiative recombination efficiency.nnnnn[1] S. Wirths, R. Geiger, N. von den Driesch, G. Mussler, T. Stoica, S. Mantl, Z. Ikonic, M. Luysberg, S. Chiussi, J. M. Hartmann et al, Nature Photonics 9,88 (2015)n[2] S. Al-Kabi, S. A. Ghetmiri, J. Margetis, T. Pham, Y. Zhou, W. Dou, B. Collier, R. Quinde, W. Du, A. Mosleh et al, Appl. Phys. Lett. 109, 171105 (2016)n[3] D. Stange, S. Wirths, R. Geiger, C. Schulte-Braucks, B. Marzban, N. von den Driesch, G. Mussler, T. Zabel, T. Stoica, J-M Hartmann et al, ACS Photonics 3, 1279 (2016)n[4] V. Reboud, A. Gassenq, N. Pauc, J. Aubin, L. Milord, Q.M. Thai, M. Bertrand, K. Guilloy, D. Rouchon, J.Rothman et al, Appl. Phys. Lett. 111, 092101 (2017)

Nanopackaging of Si(100)H Wafer for Atomic-Scale Investigations

Ultra-high vacuum (UHV) investigations have demonstrated a successful development of atomic nanostructures. The scanning tunneling microscope (STM) provides surface study at the atomic scale. However, the surface preparation is a crucial experimental step and requires a complex protocol conducted in situ in a UHV chamber. Surface contamination, atomic roughness, and defect density must be controlled in order to ensure the reliability of advanced UHV experiments. Consequently, a packaging for nanoscale devices has been developed in a microelectronic clean room environment enabling the particle density and contaminant concentration control. This nanopackaging solution is proposed in order to obtain a Si(001)-(2×1):H reconstructed surface. This surface is protected by a temporary silicon cap. The nanopackaging process consists in a direct bonding of two passivated silicon surfaces and is followed by a wafer dicing step into 1-cm2 dies. Samples can be stored, shipped, and in situ opened without any additional treatment. A specific procedure has been developed in order to open the nanopackaged samples in a UHV debonder, mounted in the load-lock chamber of a low-temperature STM system (LT-STM). Statistical large scan LT-UHV-SEM images and LT-UHV-STM images have been obtained enabling the surface study at the atomic resolution.

Stacked Nanowires FETs: Mechanical robustness evaluation for sub-7nm nodes

Stacked Nanowires FETs are proposed to replace FinFET and FDSOI for sub-7nm nodes. While most studies demonstrate the performances gain offered by such structures, mechanical stability of the suspended silicon channels needs to be considered. This paper provides a fully mechanical analytical description of nanowire stacks to explain the occurrence of buckling phenomena of silicon channels.

High-Performance Tunnel FETs on Advanced FDSOI Platform

In this chapter, we present Tunnel FETs (TFETs) obtained with a FDSOI CMOS process flow featuring High-K Metal Gate, ultrathin body compressively strained Si1-xGex (x from 0 to 30 %) based channels, and Si0.7Ge0.3 Raised SD. In-depth characterizations have been conducted to analyze the device structures (TEM, EELS for atom/layer identification, HAADF STEM GPA for strain) and device electrical performance (C(V), I D (V G ) vs. V DS and temperature, I ON , S w , tunnel extractions…). We investigate the tunneling improvements due to the different technological injection boosters: ultrathin body and gate dielectrics, strain, low band gap source, and low temperature SD anneal. The impact on I D (V G ) curves and thus on ON (and OFF) state current, subthreshold slope is presented and discussed. For the first time, TFETs with large ON current (up to 428 µA/µm) are demonstrated (with >×1,000 I ON gain vs. SOI TFETs, and >×35 I ON gain vs. best published pTFETs). Future paths towards further enhanced TFET devices are also detailed.

Controlling growth of InAs/GaAs self-assembled quantum dots to give 1.3 μm room temperature emission

We have investigated the extent to which the emission wavelength of self-assembled InAs/GaAs quantum dots can be controlled by growth parameters using conventional solid source MBE. Changing from conventionally high growth rates to a very low growth rate (LGR) and a relatively high substrate temperature, tunes the photoluminescence (PL) emission from 1.1 μm to 1.3 μm at room temperature. Atomic force micrographs obtained from uncapped samples reveal that these LGRQDs are larger, lower in density and extremely uniform in size. The improved size uniformity is reflected in the reduction of the PL linewidth from 78 meV to 22 meV. Under conditions of high excitation, emission from the ground and two excited states each separated by ∼70 meV is observed. This implies a parabolic confining potential. Time resolved photoluminescence (TRPL) measurements of dots grown under the various growth conditions yield radiative lifetimes which reflect the depth of the confining potential. A comparison of the decay times measured for the excited states show that the relaxation of carriers within the dots cannot be ascribed to phonon effects.