Jef L. van Meerbergen

Constraint analysis for code generation: basic techniques and applications in FACTS

Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by signal p processing applications and resource constraints implied by the processor architecture. In particular, limited resource availability (e.g.registers) poses a problem for traditional methods that perform code generation in separate stages (e.g., scheduling followed by register binding). This separation often results in suboptimality (or even infeasibility) of the generated solutions because it ignores the problem of phase coupling (e.g., since value lifetimes are a result of scheduling, scheduling affects the solution space for register binding). As a result, traditional methods need an increasing amount of help from the programmer (or designer) to arrive at a feasible solution. Because this requires an excessive amount of design time and extensive knowledge of the processor architecture, there is a need for automated techniques that can cope with the different kinds of contraints during scheduling. By exploiting these constraints to prune the schedule search space, the scheduler is often prevented from making a decision that inevitably violates one or more constraints. FACTS is a research tool developed for this purpose. In this paper we will elucidate the philosophy and concepts of FACTS and demonstrate them on a number of examples.

A scalable implementation of a reconfigurable WCDMA RAKE receiver

The demands in terms of processing performance, communication bandwidth and real-time throughput of new generation mobile communication applications (mobile and base-stations) are much higher than todays programmable processing architectures can deliver. On the other hand standards and market uncertainties, nonrecurring engineering costs, and lack of access to (or knowledge of) application IP will require the next generation of embedded computing platforms to be fully programmable. In terms of silicon cost and power, practical yet fully programmable embedded computing platforms are enabled by reconfigurable processors that replace fixed ASICs in current standard platforms. This paper explains the concepts behind a novel reconfigurable WCDMA rake receiver and gives benchmark results. The proposed RAKE receiver enables a high performance, yet flexible computing platform for WCDMA.

Memory arbitration and cache management in stream-based systems

With the ongoing advancements in VLSI technology the performance of an embedded system is determined to a large extent by the communication of data and instructions. This results in new methods for on- and off-chip communication and caching schemes. In this paper we use an arbitration scheme that exploits the characteristics of continuous media streams while minimizing the latency for random (e.g. CPU) memory accesses to background memory. We also introduce a novel caching scheme for a stream-based multiprocessor architecture, to limit as much as possible the amount of on-chip buffering required to guarantee the throughput of the continuous streams. With these two schemes we can build an architecture for media processing with optimal flexibility at run-time while performance guarantees can be determined at compile-time.

Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring

Wireless sensor nodes span a wide range of applications. This paper focuses on the biomedical area, more specifically on healthcare monitoring applications. Power dissipation is the dominant design constraint in this domain. This paper shows the different steps to develop a digital signal processing architecture for a single channel electrocardiogram application, which is used as an application example. The target power consumption is 100xa0μW as that is the power energy scavengers can deliver. We follow a bottleneck-driven approach: first the algorithm is tuned to the target processor, then coarse grained clock-gating is applied, next the static as well as the dynamic dissipation of the digital processor is reduced by tuning the core to the target domain. The impact of each step is quantified. A solution of 11xa0μW is possible for both radio and DSP running the electrocardiogram algorithm.

Efficient buffer capacity and scheduler setting computation for soft real-time stream processing applications

Soft real-time applications that process data streams can often be intuitively described as dataflow process networks. In this paper we present a novel analysis technique to compute conservative estimates of the required buffer capacities in such process networks. With the same analysis technique scheduler settings can be verified. Unlike many other soft real-time analysis techniques, it is guaranteed that the desired throughput is obtained for the input stream that is used to characterize the application.n Experiments with artificial test-cases indicate that the computed FIFO capacities become more conservative if the desired throughput gets closer to the maximum throughput. The run-time of our algorithm for an H263 video decoder test-case was 14 seconds.

Prophid: A Platform-Based Design Method

The continuing trendtowards higher integration densities of integrated circuits makesthe development of systems-on-a-chip possible. For well-definedapplication domains ``silicon platforms must be defined whichallow efficient, yet programmable implementations. These platformsare heterogeneous reconfigurable multiprocessor architecturessupporting a variety of communication and computation models.As a consequence designers are facing a large architecture spacewith new possibilities for new architectures. To exploit theseopportunities a better understanding of system level architecturesis necessary. A first step in this direction is to learn fromdesign exercises. Eventually this may lead towards a system leveldesign method. In this paper a multiprocessor architecture templateis presented that serves as a platform for high-throughput applications.Central to this architecture is a reconfigurable high-performanceprocessor network that uses communication concepts based on theTST-networks known from the literature. We discuss the characteristicsof the architecture template in detail. Furthermore, we willdiscuss the specification, modelling, and mapping of applicationsfor this architecture. Finally, we analyse cost and performancefigures using real implementation results.

Design of 100 µW wireless sensor nodes on energy scavengers for biomedical monitoring

Wireless sensor nodes span a wide range of applications. This paper focuses on the biomedical area, more specifically on healthcare monitoring applications. Power dissipation is the dominant design constraint in this domain. This paper shows the different steps to develop a digital signal processing architecture for a single channel electrocardiogram application, which is used as an application example. We aim for less than 100µW power consumption as that is the power energy scavengers can deliver. n nWe follow a bottleneck-driven approach, the following steps are applied: first the algorithm is tuned to the target processor, then coarse grained clock-gating is applied, next the static as well as the dynamic dissipation of the digital processor is reduced by tuning the core to the target domain. The impact of each step is quantified. A solution of around 11µW is possible for both radio and DSP with the electrocardiogram algorithm.

Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP

Impulse Radio-based Ultra-Wideband (UWB) technology is a strong candidate for the implementation of ultra low power air interfaces in low data rate sensor networks. A major challenge in UWB receiver design is the lowpower implementation of the relatively complex digital baseband algorithms that are required for timing acquisition and data demodulation. Silicon Hive offers low-power application specific instruction set processor (ASIP) solutions. In this paper we target the low-power implementation of an UWB receivers digital baseband algorithm on an ASIP, based on Silicon Hives solutions. n nWe approach the problem as follows. First we implement the algorithm on an existing ASIP and analyze the power consumption. Next we apply optimizations such as algorithmic simplification, adding a loopcache and adding custom operations to lower the dissipation of the ASIP. The resulting ASIP consumes 0.98 nJ (with a spreading factor of 16) per actual data bit, which is lower than an existing application specific integrated circuit (ASIC).