Jeffery B. Fedison

Structure of stacking faults formed during the forward bias of 4H-SiC p-i-n diodes

Using site-specific plan-view transmission electron microscopy (TEM) and light emission imaging, we have identified stacking faults formed during forward biasing of 4H-SiC p-i-n diodes. These stacking faults (SFs) are bounded by Shockley partial dislocations and are formed by shear strain rather than by the condensation of vacancies or interstitials. Detailed analysis using TEM diffraction contrast experiments reveal SFs with leading carbon-core Shockley partial dislocations as well as with the silicon-core partial dislocations observed in plastic deformation of 4H-SiC at elevated temperatures. The leading Shockley partials are seen to relieve both tensile and compressive strain during p-i-n diode operation, suggesting the presence of a complex inhomogeneous strain field in the 4H-SiC layer.

SiC Power Bipolar Transistors and Thyristors

Silicon has long been the dominant semiconductor of choice for high-voltage power electronics applications [1, 2]. However, recently, wide bandgap semiconductors, particularly SiC and GaN, have attracted much attention because they are projected to have much better performance than silicon [3]–[8] and the epi/substrate technology has matured to make device commercialization possible. SiC offers a lower intrinsic carrier concentration, a higher electric breakdown field, a higher thermal conductivity and a larger saturated electron drift velocity, when compared to silicon (see Table 1). The experimental impact ionization coefficients, usually extracted from breakdown characteristics of reverse-biased pn or Schottky junctions, are shown in Fig. 1 for both 6H- and 4H-SiC [9]–[11]. Also included in the figure is the average ionization coefficient for 6H-SiC. Such an average ionization coefficient, allows one to estimate analytically the breakdown voltage and depletion width at breakdown. (See [12] for the silicon case and [13] for 6H-SiC.) Theoretically calculated coefficients for 3C-SiC have also been performed [14]. Unlike in silicon, the hole ionization coefficient is higher than the electron coefficient in both 4H-SiC and 6H-SiC. Such trends have significant impact on bipolar transistor structure (npn vs. pnp) considerations, as will be discussed later. Also, SiC, like silicon, is an indirect semiconductor, hence SiC can have relatively long minority carrier lifetimes. Table 1 Physical properties of important semiconductors for high-volt age power devices Material E g (eV) n i (cm-3) er μn (cm2/V-s) Ec (MV/cm vsat (107 cm/s) λ (W/s mK) Direct /Indirect Si 1.1 1.5×1010 11.8 1350 0.3 1.0 1.5 I Ge 0.66 2.4×1013 16.0 3900 0.1 0.5 0.6 I GaAs 1.4 1.8×106 12.8 8500 0.4 2.0 0.5 D GaP 2.3 7.7×10–2 11.1 350 1.3 1.4 0.8 I 2H-InN 0.7 ~103 9.6 3000 1.0 2.5 D 2H-GaN 3.44 1.9×1010 9.5 900 3.3 2.5 1.3 D 3C-SiC 2.2 6.9 9.6 900 1.2 2.0 4.5 I 4H-SiC 3.26 8.2×10–9 10.0 720a 2.0 2.0 4.5 I 650c 6H-SiC 3.0 2.3×10–6 9.7 370d 2.4 2.0 4.5 I 50c Diam. 5.45 1.6×10–27 5.5 1900 5.6 2.7 20 I BN 6.0 1.5×10–31 7.1 5 10 1.0* 13 I 2H-AIN 6.2 ~10–31 8.5 300 11.7 1.7 2.85 D a mobility along a-axis, c mobility along c-axis, * estimate Open image in new window Fig. 1 Experimental impact ionization coefficients of electron and hole in 6H- and 4H-SiC [9,10]

Partial Dislocations and Stacking Faults in 4H-SiC PiN Diodes

Using plan-view transmission electron microscopy (TEM), we have identified stacking faults (SFs) in 4H-SiC PiN diodes subjected to both light and heavy electrical bias. Our observations suggest that the widely expanded SFs seen after heavy bias are faulted dislocation loops that have expanded in response to strain of the 4H-SiC film, while faulted screw or 60° threading dislocations do not give rise to widely expanded SFs. Theoretical calculations show that the expansion of SFs depends on the Peach-Koehler (PK) forces on the partial dislocations bounding the SFs, indicating that strain plays a critical role in SF expansion.

4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal

Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).