Jeffery W. Butterbaugh

Plasma–surface interactions in fluorocarbon etching of silicon dioxide

The major species present in a fluorocarbon plasma environment were simulated and independently controlled using radical and ion beams in an ultrahigh‐vacuum apparatus. The beams used in this study were chosen to determine the importance of CFx radicals in a CF4 plasma; the beams included F and CF2, with a beam of Ar+ to simulate energetic ion bombardment. Both CF2 and F enhance the etching yield of SiO2 under energetic Ar+ bombardment; however, the enhancement with F is twice that seen with CF2 at similar fluxes. When CF2 and F fluxes are used simultaneously, F dominates and the CF2 flux has little effect on the overall etching yield. Combined with previous work on Si substrates, these results are consistent with qualitative theories for SiO2/Si selectivity in fluorocarbon plasmas. Possible elementary steps in the ion‐enhanced etching process are proposed and reduced to a two‐parameter model which represents the process as ion‐enhanced neutral adsorption followed by ion‐induced reaction to form volatile ...

All Wet Stripping of Implanted Photoresist

Introduction Photoresist stripping in IC manufacturing has become more challenging. The number of photoresist levels has increased while the allowable material loss and allowable surface damage has decreased. Heavily implanted photoresist is especially challenging due to the dehydrogenated, amorphous carbon layer that forms on the surface [1]. The carbonized layer can be removed by plasma etching, or can be broken up by physical processes such as ion bombardment or the swelling of the underlying photoresist material. Physical processes, however, tend to leave residues where the carbonized resist contacts the wafer at the edges of features and particularly at the inner boundary of the wafer edge bead removal area. In addition, new plasmadoped (PLAD) implant processes provide very high implant doses and require complicated, multi-step ashing sequences for complete resist stripping. Plasma ashing processes used to strip implanted photoresist tend to oxidize the wafer surface and cause an unacceptable increase in Si material loss in subsequent processing steps. Interest in ash-free, all-wet stripping processes is driven primarily by the desire to reduce surface damage and material loss, but is also by a desire for a simplified stripping process for PLAD implants, and the elimination of a process step for all implants (wet strip/clean vs dry ash followed by a wet clean). A liquid mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), also known as “piranha” or “SPM”, can be used to remove photoresist that is unimplanted or only lightly implanted, up to about 1x10 ions/cm. When H2SO4 is mixed with H2O2, monopersulfuric acid (H2SO5 or “Caro’s acid”) is formed. Caro’s acid, and to some degree H2SO4 itself, breaks down the undamaged carbon polymer chain, eventually forming H2O and CO2 reaction products [2]. Caro’s acid, however, does not effectively remove heavily carbonized resist. Fortunately, H2O2 and Caro’s acid break down to form radicals of OH and HSO4. These radicals rapidly react with the carbonized layer, but are very short-lived (lifetime ~10s,) and so are present at a very low concentrations. Current piranha processes are heated as high as 150°C in order to accelerate radical formation and achieve sufficient reactivity and stripping rates on partially carbonized resists. If we assume Arrhenius behavior, and a radical formation activation energy of 200 kJ/mol, then the radical formation rate (and therefore concentration) will increase by over 400 times with a temperature increase from 150°C to 200°C. The rate of attack by Caro’s acid will be similarly increased. While beneficial for stripping, this rapid decay makes 200° C immersion processing impractical. In this work, achievement of freshly mixed chemistries with 200°C on-wafer temperature has enabled the wet stripping of implanted photoresist exposed to doses of over 1x10 ions/cm. Solid State Phenomena Online: 2007-11-20 ISSN: 1662-9779, Vol. 134, pp 109-112 doi:10.4028/www.scientific.net/SSP.134.109

Steam-Injected SPM Process for All-Wet Stripping of Implanted Photoresist

Photoresist stripping in IC manufacturing has become more challenging as the number of photoresist levels has increased while at the same time allowable material loss and surface damage has decreased. Heavily implanted photoresist is especially challenging due to the dehydrogenated, amorphous carbon layer that forms on the surface [1]. To facilitate implanted photoresist removal, this layer can be attacked by physical processes such as ion bombardment as part of the common dry ashing approach. However, these physical approaches can lead to surface damage and increased material loss. Another approach is to increase the reactivity of the sulfuric acid – hydrogen peroxide mixture (SPM), so that it can penetrate and dissolve the amorphous carbon layer and achieve complete photoresist removal.

Stiction-free release etch with anhydrous HF/water vapor processes

In todays MEMS fabrication, stiction remains one of the fundamental manufacturability challenges. A major step towards eliminating stiction problems is the use of a gas-phase process for the beam release. To date, an anhydrous HF/water vapor MEMS release process has been in production for two years with excellent repeatability and reliability. This stiction-free anhydrous HF/water vapor MEMS release process for accelerometers has been further characterized to determine and solve manufacturing challenges associated with the differences between aqueous-based and vapor-phase release processes. Detailed process characterization to further understand material compatibility with the HF/water vapor release process has been investigated. Various films such as oxides and nitrides of silicon, photoresist, and metals such as gold and aluminum have been characterized for their compatibility with the anhydrous HF/water vapor MEMS release process. Initial results with wafer dicing films are promising as these films show little degradation during extended vapor-phase release processes. The resistance of the wafer dicing films to the anhydrous HF/water vapor process makes it possible to complete the sacrificial oxide release process after substrates have been diced.

TRANSITION METAL CLEANING USING THERMAL BEAMS

The cleaning of transition metals including copper, nickel and iron from silicon surfaces at ambient temperature was demonstrated using various thermal beams. Sputter-deposited copper was found in two forms on silicon surfaces: uniformly dispersed copper and copper islands. At room temperature, a ClF3 beam removed the uniformly dispersed copper, but not the copper islands. Since copper–halides are not volatile at room temperature, the observation of uniformly dispersed copper removal suggested the formation of a volatile silicon–copper–halogen species. To remove the copper islands, a hot thermal dichlorosilane SiCl2H2 (DCS) beam which pyrolytically produces SiCl2 was used as a reactive silicon source. The DCS beam alone deposited SiClx on wafer surfaces suppressing complete copper removal. Exposure of this surface to ClF3 removed the SiClx deposition and copper islands from the wafer surface at room temperature. Beams containing DCS+Cl2 or DCS+F2 in which the F2 or Cl2 was also pyrolytically dissociated a...

Identification and sizing of particle defects in semiconductor-wafer processing

An experimental study of the sizing of submicron particles on semiconductor wafers is presented. The objective of the study was to determine the accuracy of a state-of-the-art optical wafer scanner, by comparing its size response with that of two well established techniques, namely, differential mobility analysis (DMA) and secondary electron microscopy (SEM). Test particles used include polystyrene–latex spheres and SiO2, Si3N4, W, and Cu particles of 64, 107, and 202 nm nominal (DMA) sizes. The scanner-indicated sizes using the oblique and normal operational modes were compared to the DMA sizes and to average sizes determined from the SEM images. Results show that the scanner-indicated size is comparable to the SEM-indicated size. However, both the scanner size and SEM size exhibit large distributions for a given nominal (DMA) size. The discrepancies are due to a combination of factors such as the effects of particle shape and material, and the presence of larger, doubly charged particles among those ana...

Uniform ultrathin oxide growth for high-k preclean

Introduction The continuous scaling of integrated circuits has driven the thickness of the gate dielectric in MOS devices to levels at which standard silicon oxide realizes excessive leakage. New materials with higher dielectric constant (high-k) than silicon oxide are being developed which can give sufficient capacitance and larger physical thickness resulting in acceptable leakage [1]. While silicon oxide gate dielectrics have been easily grown by oxidizing the silicon substrate, high-k materials must be deposited onto the silicon substrate. Surface termination prior to deposition of high-k materials has a critical impact on the performance of these films. Depositing high-k materials directly on bare silicon has been problematic leading to silicide formation and decreased electron mobility [2]. A solution to this problem is to leave the surface oxide-terminated prior to high-k deposition. However, an oxide termination layer that is too thick will defeat the purpose of depositing a high-k material, so it is important to produce a very thin oxide termination layer. This is illustrated for the case of a 12Å equivalent oxide thickness (EOT) target. Figure 1 illustrates that as the interfacial SiO2 layer becomes thinner, a thicker high-k film can be deposited while still achieving the 12Å EOT target, resulting in much lower leakage. Silicon oxidation by standard cleaning solutions and ozonated water has been utilized and studied for many years [3-9]. Ozonated water at room temperature can be used to grow a uniform oxide at saturated thicknesses of 8-10Å [5-8]. However, if is difficult to produce a uniform oxide at lesser thicknesses with ozonated water at room temperature.

Photochemical Dry Stripping of Silicon Nitride Films

UV photochemical processes have been developed for rapidly stripping films of LPCVD Si 3 N 4 in a dry reaction environment, free of plasma or plasma effluents. These processes are carried out in a vacuum reactor which allows simultaneous exposure of a substrate wafer to a polyatomic halogen gas and UV radiation. Si 3 N 4 stripping rates approaching 1000 A/min have been demonstrated for fluorine-based processes, while maintaining the bulk wafer temperature below 250°C. It has been shown that the mechanism for photochemical Si 3 N 4 etching requires both photolytic production of gas-phase F atoms and direct photon exposure of the etching surface. Selectivities between Si 3 N 4 , SiO 2 , and silicon films are controlled through UV lamp exposure, substrate temperature, and with additions of N 2 diluent and various halogen-containing gases. Selectivities for Si 3 N 4 -to-Sio 2 etching of greater than 30 can be achieved for the stripping of Si 3 N 4 LOCOS mask layers in the presence of field oxide and pad oxide layers.

Advanced Cryogenic Aerosol Cleaning: Small Particle Removal and Damage-Free Performance

The performance of a new cryogenic aerosol process was evaluated for cleaning nanoparticles and providing damage-free processing. Particle Removal Efficiency (PRE) tests conducted with wet deposited 40 nm, 30 nm and 18 nm silica particles on 300 mm wafers demonstrated cleaning efficiencies above 80%. Damage-free capability of the cryogenic aerosol process was evaluated with poly-silicon lines with an aspect ratio of approximately 9:1. These results highlight the potential of this new cryogenic aerosol to provide semiconductor device yield benefits by reducing small particulate contamination without causing pattern damage.

Selective Nitride Etching with Phosphoric and Sulfuric Acid Mixtures Using a Single-Wafer Wet Processor

Selective nitride etching in semiconductor manufacturing is currently performed in wet benches using hot orthophosphoric acid at 160-180C. This process requires silica seasoning to achieve the desired selectivity to silicon oxide. Silica seasoning in wet benches is achieved by etching blanket silicon nitride wafers prior to running productions runs. While, this method of selective silicon nitride etching has been successful in the past, particle requirements at advanced nodes [1] are driving the need for a new solution. Single wafer wet processing is proposed as a way to meet these challenging new particle specifications.