Jeffrey M. Lauerhaas

Preparation, Characterization, and Damage-Free Processing of Advanced Multiple-Gate FETs

Advanced transistor structures, such as the Multiple-Gate FET (MuGFET), offer improved shortchannel effects control compared to the bulk-Si MOSFET [1]. Hence they may be adopted in CMOS technology as early as the 32nm technology generation [2]. MuGFET current conduction is on the sidewalls of silicon fins. Thus tall fins are desirable for high drive current per unit footprint. At the same time, short channel effect (SCE) control requires narrow fin width. Therefore, for the 32nm technology generation, silicon fin width is expected to be ~15nm while silicon fin height will be ~50nm. Such tall and narrow features present unique challenges to front end cleaning and defect inspection, which must be addressed before MuGFETs can be introduced into a manufacturing environment. In this paper we present a silicon fin stability study to address these challenges. Currently available inspection and cleaning technologies in this work have demonstrated the ability to inspect with a high defect of interest capture rate and to clean the silicon fins without damage. Preand post-inspection indicate no damage to the silicon fins for each of the three cleaning technologies.

Advanced Cryogenic Aerosol Cleaning: Small Particle Removal and Damage-Free Performance

The performance of a new cryogenic aerosol process was evaluated for cleaning nanoparticles and providing damage-free processing. Particle Removal Efficiency (PRE) tests conducted with wet deposited 40 nm, 30 nm and 18 nm silica particles on 300 mm wafers demonstrated cleaning efficiencies above 80%. Damage-free capability of the cryogenic aerosol process was evaluated with poly-silicon lines with an aspect ratio of approximately 9:1. These results highlight the potential of this new cryogenic aerosol to provide semiconductor device yield benefits by reducing small particulate contamination without causing pattern damage.

Coater/developer process integration of metal-oxide based photoresist

Inpria is pioneering a novel approach to EUV photoresist. Directly patternable metal oxide thin films have shown resolution better than 10nm half-pitch, with robust etch resistance, and efficient use of photons through high EUV absorbance. Inpria’s Gen2 photoresists are cast from commonly used organic coating solvents and are developed in typical negative tone develop (NTD) organic solvents. This renders them compatible with CLEAN TRACK LITHIUS Pro-EUV coater/developer system (Tokyo Electron Limited; TEL) and solvent drains. The presence of metal in the photoresist demands additional scrutiny and process development to minimize contamination risks to other tools and wafers. In this paper, we review progress in developing coat processes that reduce metal contamination levels below typical industry levels. We demonstrate minimization of trace metals contamination from wafer-to-coater/developer, and wafer-to-wafer from the spin coat process. This will also include results from surface analyses of frontside edge exclusion and backside of wafer using best-known analytical methods. In addition, we discuss results of coat uniformity and defectivity optimization. Wet clean compatibility and dry etch rate by using conventional Si-ARC/OPL etching recipe will also be presented. In conjunction with this work, we identify potential contamination pathways and means for managing contamination risk. We furthermore review equipment compatibility issues for using Inpria’s metal oxide photoresists.

Selective Nitride Etching with Phosphoric and Sulfuric Acid Mixtures Using a Single-Wafer Wet Processor

Selective nitride etching in semiconductor manufacturing is currently performed in wet benches using hot orthophosphoric acid at 160-180C. This process requires silica seasoning to achieve the desired selectivity to silicon oxide. Silica seasoning in wet benches is achieved by etching blanket silicon nitride wafers prior to running productions runs. While, this method of selective silicon nitride etching has been successful in the past, particle requirements at advanced nodes [1] are driving the need for a new solution. Single wafer wet processing is proposed as a way to meet these challenging new particle specifications.

Single Wafer Selective Silicon Nitride Removal with Phosphoric Acid and Steam

A single wafer silicon nitride (SiN) selective etch process with an etch rate greater than 80A/min of low-pressure chemical vapor deposited (LPCVD) SiN has been developed. Previous work with a similar single wafer system utilized a mixture of sulfuric acid, phosphoric acid and steam to achieve a high SiN etch rate [1]. The process in this work relies on phosphoric acid and steam for a high SiN etch rate. In both of these applications, addition of steam doubles the SiN etch rate. The single wafer system utilizes a closed chamber design with integrated spray bar to uniformly dispense hot phosphoric acid and steam onto the wafer surface achieving within wafer non-uniformities of less than 3%. Rinsing and drying of the phosphoric acid from the wafer surface occurs in the same chamber (dry in/dry out) providing a stable, haze free wafer. Figure 1 contains a schematic of the phosphoric acid delivery and single wafer system.

Novel Wet Etching of Silicon Nitride in a Single Wafer Spin Processor

Selective etching of silicon nitride films has been an important process step in integrated circuit manufacturing for many years [1-. In the past, this process has been mainly used to remove the silicon nitride mask which protects the transistor active area during the formation of oxide isolation. Recently, this process has also been used to remove silicon nitride spacers after source and drain formation for better management of the strained channel [. Advanced device integration continues to add more steps in which the selective removal of silicon nitride is needed.