Jeffrey Bokor

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si/sub 0.4/Ge/sub 0.6/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device. The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies.

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V/sub t/) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V/sub dd/=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS).

Sub 50-nm FinFET: PMOS

High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 /spl mu/A//spl mu/m depending on the definition of the width of a double-gate device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I/sub dsat/ of 820 /spl mu/A//spl mu/m at V/sub ds/=V/sub gs/=1.2 V and T/sub ox/=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm.

Gold Nanoparticle Self-Similar Chain Structure Organized by DNA Origami

Here we demonstrate Au nanoparticle self-similar chain structure organized by triangle DNA origami with well-controlled orientation and <10 nm spacing. We show for the first time that a large DNA complex (origami) and multiple AuNP conjugates can be well-assembled and purified with reliable yields. The assembled structure could be used to generate high local-field enhancement. The same method can be used to precisely localize multiple components on a DNA template for potential applications in nanophotonic, nanomagnetic, and nanoelectronic devices.

Sub-20 nm CMOS FinFET technologies

A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current.

A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation

To extend the lower bound of power supply to ultra-low voltages (0.6 V and below), we propose a dynamic-threshold voltage MOSFET (DTMOS) built on silicon-on-insulator (SOI). The threshold voltage of DTMOS drops as the gate voltage is raised, resulting in a much higher current drive than standard MOSFET at low power supply voltages. On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low. We provide experimental results and 2-D device and mixed-mode simulations to analyze DTMOS and compare its performance with a standard MOSFET. These results verify excellent DC inverter characteristics down to V/sub dd/=0.2 V, and good ring oscillator performance down to 0.3 V for DTMOS.<<ETX>>

Diameter-Dependent Electron Mobility of InAs Nanowires

Temperature-dependent I-V and C-V spectroscopy of single InAs nanowire field-effect transistors were utilized to directly shed light on the intrinsic electron transport properties as a function of nanowire radius. From C-V characterizations, the densities of thermally activated fixed charges and trap states on the surface of untreated (i.e., without any surface functionalization) nanowires are investigated while enabling the accurate measurement of the gate oxide capacitance, therefore leading to the direct assessment of the field-effect mobility for electrons. The field-effect mobility is found to monotonically decrease as the radius is reduced to <10 nm, with the low temperature transport data clearly highlighting the drastic impact of the surface roughness scattering on the mobility degradation for miniaturized nanowires. More generally, the approach presented here may serve as a versatile and powerful platform for in-depth characterization of nanoscale, electronic materials.

A folded-channel MOSFET for deep-sub-tenth micron era

Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel folded channel transistor structure is proposed. The quasi-planar nature of this new variant of the vertical double-gate SOI MOSFETs simplified the fabrication process. The special features of the structure are: (1) a transistor is formed in a vertical ultra-thin Si fin and is controlled by a double-gate, which suppresses short channel effects; (2) the two gates are self-aligned and are aligned to the S/D; (3) S/D is raised to reduce the parasitic resistance; (4) new low-temperature gate or ultra-thin gate dielectric materials can be used because they are deposited after the S/D; and (5) the structure is quasi-planar because the Si fins are relatively short.

Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime

Thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm. Complementary low-barrier silicides were used to reduce contact and series resistance. Minimum gate-length transistors with T/sub ox/=40 /spl Aring/ show PMOS |I/sub dsat/|=270 /spl mu/A//spl mu/m and NMOS |I/sub dsat/|=190 /spl mu/A//spl mu/m with V/sub ds/=1.5 V, |V/sub g/-V/sub t/|=1.2 V and, I/sub on//I/sub off/>10/sup 4/. A simple transmission model, fitted to experimental data, is used to investigate effects of oxide scaling and extension doping.