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Dive into the research topics where Jeffrey D. Chamberlain is active.

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Featured researches published by Jeffrey D. Chamberlain.


IEEE Micro | 2015

Ivy Bridge Server: A Converged Design

Irma Esmer Papazian; Sailesh Kottapalli; Jeff Baxter; Jeffrey D. Chamberlain; Geetha Vedaraman; Brian S. Morris

The Intel microarchitecture code named Ivy Bridge (IVB) represents Intels first processor (CPU) design that services product markets from high-end desktops to mission-critical computing. With one converged design, IVB enables a rich portfolio of products and meets power, performance, and cost targets through multiple die options and configurations. IVB is the first server CPU using Intels 22-nm process technology. It achieves scalability in die size, core count, cache size, socket count, and memory size while improving power efficiency and decreasing idle power.


Archive | 2013

Virtual retry queue

Bahaa Fahim; Yen-Cheng Liu; Jeffrey D. Chamberlain


Archive | 2013

Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory

Adrian C. Moga; Vedaraman Geetha; Bahaa Fahim; Robert G. Blankenship; Yen-Cheng Liu; Jeffrey D. Chamberlain; Stephen R. Van Doren


Archive | 2014

SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS

Yen-Cheng Liu; Bahaa Fahim; Erik G. Hallnor; Jeffrey D. Chamberlain; Stephen R. Van Doren; Antonio Juan


Archive | 2010

Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline

James R. Vash; Pritpal S. Ahuja; Bongjin Jung; Jeffrey D. Chamberlain


Archive | 2016

METHOD, APPARATUS AND SYSTEM FOR MODULAR ON-DIE COHERENT INTERCONNECT

Krishnakumar Ganapathy; Yen-Cheng Liu; Antonio Juan; Steven R. Page; Jeffrey D. Chamberlain; Pau Cabre; Bahaa Fahim; Gunnar Gaubatz


Archive | 2015

DEADLOCK PREVENTION IN A PROCESSOR

Bahaa Fahim; Jeffrey D. Chamberlain; Yen-Cheng Liu


Archive | 2013

MECHANISM TO IMPROVE INPUT/OUTPUT WRITE BANDWIDTH IN SCALABLE SYSTEMS UTILIZING DIRECTORY BASED COHERECY

Henk G. Neefs; Ganesh Kumar; Vedaraman Geetha; Jeffrey D. Chamberlain; Sailesh Kottapalli; Jeffrey S. Wilder


Archive | 2015

Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement

Andrew J. Herdrich; Edwin Verplanke; Ravishankar Iyer; Christopher Gianos; Jeffrey D. Chamberlain; Ronak Singh; Julius Mandelblat; Bret L. Toll


Archive | 2015

Method, apparatus and system for optimizing cache memory transaction handling in a processor

Bahaa Fahim; Yen-Cheng Liu; Vedaraman Geetha; Jeffrey D. Chamberlain; Min Huang

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