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Vedaraman Geetha

Intel

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Publication

Featured researches published by Vedaraman Geetha.

Archive | 2013

High performance interconnect

Robert J. Safranek; Robert G. Blankenship; Venkatraman Iyer; Jeff Willey; Robert Beers; Darren S. Jue; Arvind Kumar; Debendra Das Sharma; Jeffrey C. Swanson; Bahaa Fahim; Vedaraman Geetha; Aaron T. Spink; Fulvio Spagna; Rahul R. Shah; Sitaraman V. Iyer; William H. Nale; Abhishek Das; Simon P. Johnson; Yuvraj S. Dhillon; Yen-Cheng Liu; Raj K. Ramanujan; Robert A. Maddox; Herbert H. J. Hum; Ashish Gupta

Archive | 2013

Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines

Adrian C. Moga; Malcolm Mandviwalla; Vedaraman Geetha; Herbert H. J. Hum

Archive | 2013

HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL

Robert G. Blankenship; Bahaa Fahim; Robert Beers; Yen-Cheng Liu; Vedaraman Geetha; Herbert H. J. Hum; Jeff Willey

Archive | 2013

Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory

Adrian C. Moga; Vedaraman Geetha; Bahaa Fahim; Robert G. Blankenship; Yen-Cheng Liu; Jeffrey D. Chamberlain; Stephen R. Van Doren

Archive | 2013

METHOD, APPARATUS AND SYSTEM FOR HANDLING CACHE MISSES IN A PROCESSOR

Bahaa Fahim; Samuel D. Strom; Vedaraman Geetha; Robert G. Blankenship; Yen-Cheng Liu; Krishnakumar Ganapathy; Cesar Maldonado

Archive | 2017

Cpu remote snoop filtering mechanism for field programmable gate array cache

Bahaa Fahim; Samuel D. Strom; George H. Huang; Vedaraman Geetha; Yen-Cheng Liu

Archive | 2011

Dynamically routing data responses directly to requesting processor core

Allen J. Baum; Sailesh Kottapalli; Vedaraman Geetha

Archive | 2013

MECHANISM TO IMPROVE INPUT/OUTPUT WRITE BANDWIDTH IN SCALABLE SYSTEMS UTILIZING DIRECTORY BASED COHERECY

Henk G. Neefs; Ganesh Kumar; Vedaraman Geetha; Jeffrey D. Chamberlain; Sailesh Kottapalli; Jeffrey S. Wilder

Archive | 2015

Method, apparatus and system for optimizing cache memory transaction handling in a processor

Bahaa Fahim; Yen-Cheng Liu; Vedaraman Geetha; Jeffrey D. Chamberlain; Min Huang

Archive | 2013

Cache coherency apparatus and method minimizing memory writeback operations

Jeffrey D. Chamberlain; Vedaraman Geetha; Robert G. Blankenship; Yen-Cheng Liu; Adrian C. Moga; Herbert H. J. Hum; Sailesh Kottapalli

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Yen-Cheng Liu

Intel

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Bahaa Fahim

Intel

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Robert G. Blankenship

Intel

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Herbert H. J. Hum

Intel

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Jeffrey D. Chamberlain

Intel

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Sailesh Kottapalli

Intel

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Adrian C. Moga

Intel

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Henk G. Neefs

Intel

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Jeff Willey

Intel

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Robert Beers

Intel

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