Sailesh Kottapalli

A 45 nm 8-Core Enterprise Xeon¯ Processor

This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon® EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the unterminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.

Power reduction techniques for an 8-core xeon ® processor

This paper presents the power reduction and management techniques for the 45nm, 8-core Nehalem-EX processor. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. Clock and power gating minimize power consumed by disabled blocks. An on-die microcontroller manages voltage and frequency operating points, as well as power and thermal events. Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.

Westmere-EX: A 20 thread server CPU

This article consists of a collection of slides from the authors conference presentation on Intels Westmere-EX, a 20 thread server CPU family of products. Some of the specific topics discussed include: the special features, system specifications, and system design of the Westmere-EX; system architecture; applications for use; platforms supported; processing capabilities; and targeted markets.

Ivy Bridge Server: A Converged Design

The Intel microarchitecture code named Ivy Bridge (IVB) represents Intels first processor (CPU) design that services product markets from high-end desktops to mission-critical computing. With one converged design, IVB enables a rich portfolio of products and meets power, performance, and cost targets through multiple die options and configurations. IVB is the first server CPU using Intels 22-nm process technology. It achieves scalability in die size, core count, cache size, socket count, and memory size while improving power efficiency and decreasing idle power.

Nahalem-EX CPU architecture

Presents a collection of slides covering the following topics: Nehalem-EX CPU architecture; processor architecture; CPU dataflow; last level cache; system agent; coherence agent; memory controller; and system interconnect.