Jeffrey D. Gilbert

Over one million TPCC with a 45nm 6-core Xeon® CPU

This paper describes the 6-core Xeon® 7400 series processor family, codename Dunnington, designed for a broad range of highly power efficient servers. The processor consists of three dual-core 45nm Core™ processors [1] and a shared inclusive 16MB L3 cache (LLC) integrated on a monolithic 503mm2 die. The system interface is FSB based with the I/Os incorporated into the center of the die. Figure 3.8.1 shows the chip floorplan. The core-to-FSB connection is replaced with an on-die low-latency uncore interface. The uncore arbitrates among core, LLC, and external bus requests. The processor has 1.9B transistors and is implemented in 45nm CMOS using high-κ metal-gate transistors and nine copper interconnect layers [2]. The maximum thermal design power is 130W.

The tulsa processor: A dual core large shared-cache Intel® Xeon processor 7000 sequence for the MP server market segment

This article consists of a collection of slides from the authors conference presentation on the Tulsa Processor from Intel. Some of the specific topics discussed include: the special features of the Tulsa processor; applications for its use; processing capabilities; targeted markets for its deployment; paths to multi-core designs; options for multiple core processing; the Tulsa engineering experience based on product implementation and use; system architecture; and tested performance output results.