Jeffrey Draper

A Comprehensive Analytical Model for Wormhole Routing in Multicomputer Systems

An analytical model for obtaining performance measures in multicomputer networks that use wormhole routing is presented. Unlike previous wormhole routing models, the model introduced in this paper is accurate and quite simple. The model is validated through flit-level simulation experiments and is sufficiently general to be extended for several networks, including k-ary n-cubes, and related routing paradigms, such as virtual cut-through, The value of this model is exhibited through its application to current networks to indicate cost-effective augmentations which result in significant performance improvements.

The architecture of the DIVA processing-in-memory chip

The DIVA (Data IntensiVe Architecture) system incorporates a collection of Processing-In-Memory (PIM) chips as smart-memory co-processors to a conventional microprocessor. We have recently fabricated prototype DIVA PIMs. These chips represent the first smart-memory devices designed to support virtual addressing and capable of executing multiple threads of control. In this paper, we describe the prototype PIM architecture. We emphasize three unique features of DIVA PIMs, namely, the memory interface to the host processor, the 256-bit wide datapaths for exploiting on-chip bandwidth, and the address translation unit. We present detailed simulation results on eight benchmark applications. When just a single PIM chip is used, we achieve an average speedup of 3.3X over host-only execution, due to lower memory stall times and increased fine-grain parallelism. These 1-PIM results suggest that a PIM-based architecture with many such chips yields significantly higher performance than a multiprocessor of a similar scale and at a much reduced hardware cost.

Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs

The range of SRAM multi-bit upsets (MBU) in sub-100 nm technologies is characterized using irradiation tests on two prototype ICs, developed in 90 nm commercial processes. Results reveal that MBU, as large as 13-bit, can occur in these technologies, limiting the efficacy of conventional SEC-DED error-correcting codes (ECC). A double-error correcting (DEC) ECC implementation technique suitable for SRAM applications is presented. Results show that this DEC scheme reduces errors by 98.5% compared to only 44% reduction by conventional SEC-DED ECC.

Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge (Qcrit) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X ldquoprocess generationrdquo scaling penalty in area, speed, and power.

Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM

Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. In this paper the authors investigate the critical charge (Qcrit) required to upset a 6T SRAM cell designed in a commercial 90nm process. The authors characterize Qcrit using different current models and show that there are significant differences in Qcrit values depending on which models are used. Discrepancies in critical charge characterization are shown to result in under-predictions of the SRAMs associated soft error rate as large as two orders of magnitude. For accurate Qcrit calculation, it is critical that 3D device simulation is used to calibrate the current pulse modeling heavy ion strikes on the circuit, since the stimuli characteristics are technology feature size dependant. Current models with very fast characteristic timing parameters are shown to result in conservative soft error rate predictions; and can assertively be used to model ion strikes when 3D simulation data is not available.

DF-DICE: a scalable solution for soft error tolerant circuit design

The delay filtered dual interlocked storage cell (DF-DICE) offers a scalable solution in different radiation environments for soft error mitigation. The area and speed performance for five different single event transient thresholds have been evaluated. The results show that the cost of soft error mitigation is minimal for terrestrial environments (overall area penalty less than 14% and speed penalty within 6% for flip-flop based typical designs) while it is larger for space environments (overall area penalty up to 30% and speed penalty up to 13% for flip-flop based typical designs). The logic of a conventional application specific integrated circuit (ASIC) can easily be converted to a soft-error tolerant design by replacing the existing storage elements with the respective DF-DICE elements

DEC ECC design to improve memory reliability in Sub-100nm technologies

Exacerbated SRAM reliability issues, due to soft errors and increased process variations in sub-100 nm technologies, limit the efficacy of conventionally used error correcting codes (ECC). The double error correcting (DEC) BCH codes have not found favorable application in SRAMs due to non-alignment of their block sizes to typical memory word widths and particularly due to the large multi-cycle latency of traditional iterative decoding algorithms. This work presents DEC code design that is aligned to typical memory word widths and a parallel decoding implementation approach that operates on complete memory words in a single cycle. The practicality of this approach is demonstrated through ASIC implementations, in which it incurs only 1.4 ns and 2.2 ns decoding latencies for 16- and 64-bit words, respectively, using 90 nm ASIC technology. A comparative analysis between conventionally used ECC and DEC ECC for reliability gains and costs incurred has also been performed.

A continuous-time common-mode feedback circuit (CMFB) for high-impedance current-mode applications

A continuous-time common-mode feedback circuit (CMFB) is presented. A two-stage high-gain architecture is used to stabilize and minimize the offset of the common-mode voltage. A long-channel differential-difference amplifier (DDA) input stage enables this CMFB circuit to have a wide input voltage range without a serious linearity problem. A special compensation scheme enables this circuit to be used in high-impedance current-mode systems without a stability problem. This circuit has been implemented within a continuous-time switched-current /spl Sigma//spl Delta/ modulator in a 2 /spl mu/m CMOS process. It achieves a /spl plusmn/1 V input voltage range with an active area of 100 /spl mu/m/spl times/60 /spl mu/m and a power dissipation of 270 /spl mu/W from a single 5 V power supply.

The DF-dice storage element for immunity to soft errors

This paper describes the delay filtered dual interlocked storage cell, which is immune to single event transients on any of the inputs and single event upsets within the storage cell. The increase in area and speed of an application specific integrated circuit (ASIC) employing the proposed cells are proportional to the targeted single-event transient (SET) pulse-width. A standard ASIC can easily be converted to a soft-error tolerant design by simply replacing all the storage elements with the proposed cells. The area and speed performance of the proposed cells targeted for an 800ps wide SET have been evaluated. The resulting designs are immune to soft-errors with acceptable area penalty and modest degradation in speed.

Duty cycle measurement and correction using a random sampling technique

A specific value of duty cycle of an on-chip clock or signal often becomes of extreme significance in VLSI circuits like DRAMs, dynamic/domino pipelined circuits, pipelined analog-to-digital converters (ADC) and serializer/deserializer (SERDES) circuits, which are sensitive to the duty cycle or where operations are synchronized with both transitions of the clock. This paper introduces a novel idea based on a random sampling technique of inferential statistics for measurement and local correction of the duty cycle of high-speed on-chip signals. The high measurement accuracy achievable through the proposed random sampling technique provides a way to correct the duty cycle with a maximum error of less than half the smallest delay resolution unit available for correction. An input signal with duty cycle from 30% to 70% can be adjusted to a wide range of values within this range using a purely digital, area-efficient standard cell based design. Our experimental results gathered though extensive simulations of the proposed circuit manifest a very close correlation to the expected theoretical results.