Louis Luh

A high-speed fully differential current switch

A high-speed differential-mode current switch is presented. The clock-feedthrough effect is reduced by swing-reduced drivers (SRDs) and neutralized by dummy transistors. With the use of SRDs, the switching transistors never operate in the triode region, which provides good matching of capacitance between the switching transistors and dummy transistors. The SRDs also reduce the possible large current spikes on the outputs of the current switch. Analysis shows this current switch is ideal for high-speed current-mode signal processing. A continuous-time switched-current /spl Sigma//spl Delta/ modulator using these current switches has been implemented in a 2 /spl mu/m CMOS process and achieved a 59 dB dynamic range with a 50 MHz clock.

A continuous-time common-mode feedback circuit (CMFB) for high-impedance current mode application

A continuous-time common-mode feedback circuit (CMFB) is presented. A two-stage high-gain architecture is used to minimize the offset of the common-mode voltage. A special compensation scheme enables this circuit to be used in high-impedance current-mode systems without a stability problem. Simulation and testing results show the superior performance of this circuit. It is proven to be an ideal common-mode feedback circuit for systems which require an accurate and stable common-mode voltage. This circuit has been implemented in a continuous-time switched-current /spl Sigma//spl Delta/ modulator with a 2 /spl mu/m CMOS process. With a 50 MHz clock, the modulator has achieved a 60 dB dynamic range in a 1 MHz bandwidth.

A novel fully integrated fan controller for advanced computer systems

A low-cost, high-efficiency, compact architecture of a PWM (pulse-width-modulation) drive fan controller is designed for use in an embedded multicomputer system with an integrated hierarchical thermal management scheme. This pure digital design yields lower cost and higher conventional linear drive fan providing the functionality and advantages of PWM drive fan controllers. The implementation and system integration of this circuit is also described in this paper.

A novel model for on-chip heat dissipation

This paper presents an analytical model for on-chip heat dissipation in VLSI design. A chip and its test configuration also are developed to verify modeling results. The model and chip are representative of general IC packages. Our research shows that circuit location on a chip determines its default offset temperature and heat transport properties, which must be considered for accurate prediction of junction temperature and electrothermal analysis. The model yields insights about on-chip heat dissipation, which are very useful for mixed-signal VLSI designs and circuit reliability analysis.

A continuous-time switched-current /spl Sigma//spl Delta/ modulator with reduced loop delay

A novel architecture for a second-order continuous-time switched-current /spl Sigma//spl Delta/ modulator is presented. The loop delay is reduced by predicting the states of the second integrator and feeding the predicted states to the comparator. The predicted states are generated by summing three scaled current mode signals. A gain-manager is used to accurately control the integrator gain to generate the predicted states and stabilize the system. A newly designed high-speed current-mode comparator is capable of summing the three scaled current inputs and comparing them. With a 50 MHz sampling rate, it has achieved 60 dB dynamic range (10-bit) at 1 MHz. The modulator has been fabricated in a 2 /spl mu/m CMOS process with an active area of 0.37 mm/sup 2/. The power dissipation is 16.6 mW from a 5 V single power supply.

A 50-MHz continuous-time switched-current /spl Sigma//spl Delta/ modulator

A new architecture of second-order continuous-time switched-current /spl Sigma//spl Delta/ modulator is presented. A reference current generator is used in the second stage to solve the scaling problem. A novel current switch is designed to minimize the clock feedthrough problem and increase the operating speed. With a 50 MHz sampling rate, it has achieved 50 dB dynamic range (8-bit) at 1 MHz. This modulator has been fabricated in a 2 /spl mu/m CMOS process with an active area of 0.37 mm/sup 2/. The power dissipation is 15 mW.

A high-speed high-resolution CMOS current comparator

A high-speed high-resolution CMOS current comparator is presented. A dynamic gain boosting stage is used to maximize the comparator gain while maintaining acceptable power consumption. A PMOS regenerative amplifier together with a source follower stage is used to reduce the comparison time and increase the resolution. The charge kick-back (feedback) effect is minimized by properly resetting a few internal nodes and by using an input stage. This circuit has been implemented in a 1.2 /spl mu/m CMOS process and achieved 100 nA resolution at a sampling rate up to 110 MHz and 170 nA resolution up to 140 MHz with a single 5 V power supply.

Area-efficient area pad design for high pin-count chips

This paper presents an area pad layout method to efficiently reduce the space required for interconnection pads and pad drivers. Unlike peripheral pads, area pads use only the top metal layer and therefore allow active circuitry to be laid out underneath. With identical functional elements grouped together, a group of pad drivers share the same well and can be placed tightly together. The use of silicided diffusion reduces the well contact to diffusion contact spacing requirement. By taking advantage of this spacing requirement and using serpentine gate layout, a drivers size can be effectively reduced without reducing the driving capacity. An embedded multicomputer router interface chip has been implemented using these techniques and has achieved 554 pads in a 9 mm/spl times/6 mm chip with a 0.8 /spl mu/m single-poly 3-metal N-well CMOS process.

A Zener-diode-activated ESD protection circuit for sub-micron CMOS processes

A Zener-diode-activated electrostatic discharge (ESD) protection circuit is implemented in a 0.5 /spl mu/m CMOS process. This ESD circuit uses a substrate p-n-p transistor with its base connected to a Zener diode to discharge the electrostatic energy. The Zener diode implementation utilizes a silicide block capability to avoid short circuits in the active area. Its performance has been tested by the human body model and a high-speed ESD test. Its latchup-free characteristic makes it an ideal circuit for ESD protection of I/O pads, ESD clamping between power rails, poly-antenna effect protection, and overshoot attenuation.

A high-speed digital comb filter for /spl Sigma//spl Delta/ analog-to-digital conversion

A new approach for implementing a digital decimator for high-speed /spl Sigma//spl Delta/ modulators is presented. With the use of carry-saved adders, this decimator is able to operate at high speeds while maintaining the same throughput. By using systematic modular design, this filter can be easily designed and implemented with any order and any length, which greatly reduces the time and effort for circuit design. A prototype of a fourth-order length-16 digital comb filter has been implemented with a 1.2 /spl mu/m standard CMOS process. With a single 5 V power supply, this filter can operate at a frequency up to 115 MHz. The power consumption is about 35 mW and the active area is 1083/spl times/965 /spl mu/m/sup 2/.