Jeffrey Marks

Overview of atomic layer etching in the semiconductor industry

Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting. ALE has been studied in the laboratory for more than 25 years. Today, it is being driven by the semiconductor industry as an alternative to continuous etching and is viewed as an essential counterpart to atomic layer deposition. As we enter the era of atomic-scale dimensions, there is need to unify the ALE field through increased effectiveness of collaboration between academia and industry, and to help enable the transition from lab to fab. With this in mind, this article provides defining criteria for ALE, along with clarification of some of the terminology and assumptions of this field. To increase understanding of the process, the mechanistic understanding is described for the silicon ALE case study, including the advantages of plasma-assisted processing. A historical overview spanning more than 25 years is provided for silicon, as well as ALE studies on oxides, III–V c...

Predicting synergy in atomic layer etching

Atomic layer etching (ALE) is a multistep process used today in manufacturing for removing ultrathin layers of material. In this article, the authors report on ALE of Si, Ge, C, W, GaN, and SiO2 using a directional (anisotropic) plasma-enhanced approach. The authors analyze these systems by defining an “ALE synergy” parameter which quantifies the degree to which a process approaches the ideal ALE regime. This parameter is inspired by the ion-neutral synergy concept introduced in the 1979 paper by Coburn and Winters [J. Appl. Phys. 50, 5 (1979)]. ALE synergy is related to the energetics of underlying surface interactions and is understood in terms of energy criteria for the energy barriers involved in the reactions. Synergistic behavior is observed for all of the systems studied, with each exhibiting behavior unique to the reactant–material combination. By systematically studying atomic layer etching of a group of materials, the authors show that ALE synergy scales with the surface binding energy of the bu...

New generations of tools sets that enable FDSOI and 3-D tri-gate technologies

Today no insurmountable obstacles are foreseen inhibiting scaling logic devices to the 10nm node. Cost effective processes and equipment sets have been developed that allow both 3-D Tri-Gate and Ultra-Thin Body SOI integration schemes to be scaled. This allows the equipment industry to focus on innovations of new material and their integration into cost effective tool sets in time for high volume manufacturing in sub 10nm node technology. In this paper we review various process challenges the equipment industry overcame to enable the 3-D Tri-Gate and Ultra-Thin Body SOI architecture in partnership with integrated device manufactures.

Patterning in the era of atomic scale fidelity

Relentless scaling of advanced integrated devices drives feature dimensions towards values which can be expressed in small multiples of the lattice spacing of silicon. One of the consequences of dealing with features on such an atomic scale is that surface properties start to play an increasingly important role. To encompass both dimensional as well as compositional and structural control, we introduce the term “atomic scale fidelity.” In this paper, we will discuss the challenges as well as new solutions to achieve atomic scale fidelity for patterning etch processes. Fidelity of critical dimensions (CD) across the wafer is improved by means of the Hydra Uniformity System. Wafer, chip and feature level atomic scale fidelity such as etch rate uniformity, aspect ratio dependent etching (ARDE) /1/, selectivity and surface damage can be addressed with emerging atomic layer etching (ALE) approaches /2/.