Samantha Tan

Overview of atomic layer etching in the semiconductor industry

Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting. ALE has been studied in the laboratory for more than 25 years. Today, it is being driven by the semiconductor industry as an alternative to continuous etching and is viewed as an essential counterpart to atomic layer deposition. As we enter the era of atomic-scale dimensions, there is need to unify the ALE field through increased effectiveness of collaboration between academia and industry, and to help enable the transition from lab to fab. With this in mind, this article provides defining criteria for ALE, along with clarification of some of the terminology and assumptions of this field. To increase understanding of the process, the mechanistic understanding is described for the silicon ALE case study, including the advantages of plasma-assisted processing. A historical overview spanning more than 25 years is provided for silicon, as well as ALE studies on oxides, III–V c...

Predicting synergy in atomic layer etching

Atomic layer etching (ALE) is a multistep process used today in manufacturing for removing ultrathin layers of material. In this article, the authors report on ALE of Si, Ge, C, W, GaN, and SiO2 using a directional (anisotropic) plasma-enhanced approach. The authors analyze these systems by defining an “ALE synergy” parameter which quantifies the degree to which a process approaches the ideal ALE regime. This parameter is inspired by the ion-neutral synergy concept introduced in the 1979 paper by Coburn and Winters [J. Appl. Phys. 50, 5 (1979)]. ALE synergy is related to the energetics of underlying surface interactions and is understood in terms of energy criteria for the energy barriers involved in the reactions. Synergistic behavior is observed for all of the systems studied, with each exhibiting behavior unique to the reactant–material combination. By systematically studying atomic layer etching of a group of materials, the authors show that ALE synergy scales with the surface binding energy of the bu...

Integrated approach to improving local CD uniformity in EUV patterning

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

The influence of post-etch InGaAs fin profile on electrical performance

The onset of the 22 nm node introduced three dimensional tri-gate transistors into high-volume manufacturing for improved electrostatics. The next generations of fin nMOSFETs are predicted to be InGaAs based. Due to the ternary nature of InGaAs, stoichiometric and structural modifications could affect the electronic properties of the etched fin. In this work we have created InGaAs fins down to 35 nm fin width with atomic surface structure kept nearly identical to that of the bulk. Our experimental and simulation results show the impact of surface stoichiometry and fin profile on electrical performance.

Atomic layer etching of GaN and AlGaN using directional plasma-enhanced approach

The directional atomic layer etching (ALE) of GaN and AlGaN has been developed. The GaN ALE process consists of cyclic Cl2 plasma chemisorption and Ar ion removal. The etch per cycle (EPC) was 0.4 nm within the self-limiting regime, which is 50 to 100 V. The root-mean-square surface roughness R RMS was 0.6 nm, which was improved from an initial roughness of 0.8 nm. For AlGaN ALE, BCl3 was added to the chlorine step to obtain a smooth surface with R RMS of 0.3 nm and stoichiometry similar to the initial sample. The ultra smooth surface obtained by etching is promising for use in next-generation power devices.

Applying sputtering theory to directional atomic layer etching

Plasma assisted atomic layer etching (ALE) has recently been introduced into manufacturing of 10 nm logic devices. This implementation of ALE is called directional ALE because ions transfer momentum to the etching surface during the removal step. Plasma assisted directional ALE can be described as sputtering of a thin modified layer on the surface of the unmodified material. In this paper, the authors introduce a collision cascade based Monte Carlo model based on sputtering theory which has evolved for over 50 years [P. Sigmund, Thin Solid Films 520, 6031 (2012)]. To test the validity of this approach, calculated near threshold argon ion sputtering yields of silicon and chlorinated silicon are compared to published experimental data. The calculated ALE curve for Cl2/Ar ALE of tantalum is in good agreement with the experiment. The model was used to predict the presence of salient sputtering effects such as ion mass and impact angle dependence, as well as redeposition in directional ALE. Finally, the author...

Atomic Layer Etching: Rethinking the Art of Etch

Atomic layer etching (ALE) is the most advanced etching technique in production today. In this Perspective, we describe ALE in comparison to long-standing conventional etching techniques, relating it to the underlying principles behind the ancient art of etching. Once considered too slow, we show how leveraging plasma has made ALE a thousand times faster than earlier approaches. While Si is the case study ALE material, prospects are better for strongly bound materials such as C, Ta, W, and Ru. Among the ALE advantages discussed, we introduce an ALE benefit with potentially broad application-the ALE smoothing effect-in which the surface flattens. Finally, regarding its well-established counterpart of atomic layer deposition (ALD), we discuss the combination of ALE and ALD in tackling real world challenges at sub-10 nm technology nodes.

Optimization of Cu/Low-k Dual Damascene Post-Etch Residue and TiN Hard Mask Removal

For advanced technology nodes TiN hard mask integration into Cu/low-k via/trench DD process requires the mask to be fully stripped after DD etching. The one-step H2O2 containing wet chemical clean aiming to removing TiN mask often failed to simultaneously clean etch residue. We developed more reliable two-step wet chemical process combining a solvent-based post-etch residue clean followed by a solvent/H2O2 mixture strip for TiN mask removal. Bath lifetime optimization was also demonstrated.

Patterning in the era of atomic scale fidelity

Relentless scaling of advanced integrated devices drives feature dimensions towards values which can be expressed in small multiples of the lattice spacing of silicon. One of the consequences of dealing with features on such an atomic scale is that surface properties start to play an increasingly important role. To encompass both dimensional as well as compositional and structural control, we introduce the term “atomic scale fidelity.” In this paper, we will discuss the challenges as well as new solutions to achieve atomic scale fidelity for patterning etch processes. Fidelity of critical dimensions (CD) across the wafer is improved by means of the Hydra Uniformity System. Wafer, chip and feature level atomic scale fidelity such as etch rate uniformity, aspect ratio dependent etching (ARDE) /1/, selectivity and surface damage can be addressed with emerging atomic layer etching (ALE) approaches /2/.

Clean Process Mechanism of HKMG during N-PMOS Patterning

Chemical and physical modifications of photoresist and BARC during plasma patterning process on HKMG structure can cause residual defects and yield loss that challenges the subsequent wet cleaning process to resolve this issue. The chemical behavior of materials post dry etching and wet clean was systematically studied by various surface analytical techniques including STEM-EELS, XPS and AES. With a greater understanding of the etching and clean mechanisms, a combined aqueous/solvent cleaning method was developed and tested on a spin clean tool to effectively clean etching by-products. A significant improvement of yield with the application of the new cleaning approach has been observed.