Saurav Bandyopadhyay

Platform Architecture for Solar, Thermal, and Vibration Energy Combining With MPPT and Single Inductor

A 0.35µm CMOS energy processor with multiple inputs from solar, thermal and vibration energy sources is presented. Dual-path architecture for energy harvesting is proposed that has up to 13% higher conversion efficiency compared to the conventional two stage storage-regulation architecture. To minimize the cost and form factor, a single inductor has been time shared for all converters. A novel low power maximum power point tracking (MPPT) scheme with 95% tracking efficiency is also introduced.

energy extraction from the biologic battery in the inner ear

Endocochlear potential (EP) is a battery-like electrochemical gradient found in and actively maintained by the inner ear. Here we demonstrate that the mammalian EP can be used as a power source for electronic devices. We achieved this by designing an anatomically sized, ultra-low quiescent-power energy harvester chip integrated with a wireless sensor capable of monitoring the EP itself. Although other forms of in vivo energy harvesting have been described in lower organisms, and thermoelectric, piezoelectric and biofuel devices are promising for mammalian applications, there have been few, if any, in vivo demonstrations in the vicinity of the ear, eye and brain. In this work, the chip extracted a minimum of 1.12 nW from the EP of a guinea pig for up to 5 h, enabling a 2.4 GHz radio to transmit measurement of the EP every 40–360 s. With future optimization of electrode design, we envision using the biologic battery in the inner ear to power chemical and molecular sensors, or drug-delivery actuators for diagnosis and therapy of hearing loss and other disorders.

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Digital baseband processors [1] in portable devices today are able to operate off voltages of 1V and less. Efficient DC-DC converters are required to power these ICs from Li-ion batteries with a voltage range of 2.8 to 4.2V. This is done by a discrete power management IC (PMIC) capable of handling the high battery voltage. However, there is significant push in integrating the PMIC module with the baseband processor implemented in scaled technologies thereby reducing the number of system-level components. This paper presents the circuit techniques used in a 45nm CMOS DC-DC converter with high battery-voltage handling capability.

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A wireless sensor that is powered from the endocochlear potential (EP), a 70-to-100mV bio-potential inside the mammalian ear, has been demonstrated in [1]. Due to the anatomical size and physiological constraints inside the ear, a maximum of 1.1 to 6.25nW can be extracted from the EP. The nanowatt power budget of the sensor gives rise to unique challenges with power conversion efficiency and quiescent current reduction in the power management unit (PMU). While [1] presents the system aspects of the biomedical harvesting including the biologic interface and system measurements, this work presents the details of the nanowatt PMU required to power the electronics. More specifically, it focuses on the low-power circuit design techniques needed to realize a nW power converter that is applicable to a broad spectrum of emerging biomedical applications with ultra-low energy-harvesting sources.

A to 100 mA DC–DC Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45 nm CMOS

Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate for an integrated energy conversion solution that eliminates the need for inductors [2,3]. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to the overhead of the control circuit. Reconfigurable SC converters supporting multi-gain settings have been proposed to allow efficient operation across wide output range [2,4]. Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection.

23.2 A 1.1nW energy harvesting system with 544pW quiescent power for next-generation implants

This paper presents the design of a narrowband transmitter and antenna system that achieves an average power consumption of 78 pW when operating at a duty-cycled data rate of 1 bps. Fabricated in a 0.18 μm CMOS process, the transmitter employs a direct-RF power oscillator topology where a loop antenna acts as a both a radiative and resonant element. The low-complexity single-stage architecture, in combination with aggressive power gating techniques and sizing optimizations, limited the standby power of the transmitter to only 39.7 pW at 0.8 V. Supporting both OOK and FSK modulations at 2.4 GHz, the transmitter consumed as low as 38 pJ/bit at an active-mode data rate of 5 Mbps. The loop antenna and integrated diodes were also used as part of a wireless power transfer receiver in order to kick-start the system power supply prior to energy harvesting operation.

A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors

With the advent of reliable, high brightness and high efficacy LEDs, the lighting industry is expected to see a significant growth in the near future. However, for LEDs to completely replace the traditional incandescent and CFL bulbs, the power converters within the LED drivers need to be miniaturized. Superior figure of merit (Rds,ONxQg) of Gallium Nitride (GaN) FETs over Silicon FETs [1] can enable both high efficiency and high frequency operation, thereby making power converters smaller, more efficient and reliable. By using integrated controllers and drivers, the number of components on the driver PCB can be reduced, further miniaturizing the driver. This work focuses on demonstrating a small form factor, high efficiency offline LED driver using GaN FETs with an integrated gate driver and controller circuit implemented on a 0.35μm CMOS process with 3.3V/15V voltage handling capability.

A Sub-nW 2.4 GHz Transmitter for Low Data-Rate Sensing Applications

This paper presents an ultra-low-standby-power radio transmitter that was designed for applications with extreme energy storage and/or energy harvesting constraints. By utilizing aggressive power gating techniques within a low-complexity architecture featuring only a single RF stage, the transmitter achieved a standby power consumption of 39.7 pW. The architecture employed a direct-RF power oscillator that featured an on-board loop antenna that functioned as both the resonant and radiative element. Supporting both OOK and FSK modulations, the transmitter consumed 38 pJ/bit at an instantaneous data rate of 5 Mb/s. After duty-cycling down to an average data rate of 1 b/s, the transmitter consumed an average power of 78 pW.

90.6% efficient 11MHz 22W LED driver using GaN FETs and burst-mode controller with 0.96 power factor

This paper presents an accurate loss model of a Quasi-Square Wave (QSW) buck converter and analyzes the efficiency benefits of GaN FETs over Silicon super-junction FETs. A design methodology and optimization strategy is presented while accounting for the FET Figures-of-Merit (FoM). The model uses computational techniques to account for non-linear device capacitances and precisely predicts the FET on times, resonant intervals and switching frequency required for ZVS operation. Analyses show the FET RDS,ON-QOss FoM has the maximum impact in the efficiency affecting both FET and inductor losses and a FoM dependent optimal RDS,ON exists for which the FET conduction losses balance the inductor losses. The loss model is validated by two QSW buck converters designs operating at 36W using GaN and Silicon FETs, each optimized to maximize their end-to-end efficiencies.

A 78 pW 1 b/s 2.4 GHz radio transmitter for near-zero-power sensing applications

This paper presents a new isolated ac-dc power converter achieving both high power factor and converter miniaturization suitable for many low power ac-dc applications. The proposed ac-dc converter architecture comprises a line-frequency rectifier, a stack of capacitors, a set of regulating converters, and a multi-input isolated bus converter. Among many suitable circuit implementations, the prototype system utilizes the resonant-transition buck converter as a regulating converter, and the capacitively-aided isolated bus converter for the isolated bus converter. The converter is miniaturized by operating at high frequency (1–10 MHz range), and it buffers the ac-line frequency energy with a pair of stacked ceramic capacitors (1 μΕ and 150 μΕ, 100 V rating) without a requirement for electrolytic capacitors. The prototype converter is implemented to operate from 120 Vac to 12 V, and up to 50 W output as an example isolated ac-dc converter for power supply applications. The prototype converter demonstrates with 88 % efficiency and 0.86 power factor, and provides 50 W/in3 power density, which is five times higher than the power density of typical conventional designs.