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Dive into the research topics where Jeffrey P. Soreff is active.

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Featured researches published by Jeffrey P. Soreff.


Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems | 2002

Aggressive crunching of extracted RC netlists

Vasant B. Rao; Jeffrey P. Soreff; Ravichander Ledalla; Fred L. Yang

This paper presents a short-and-update technique for resistors (possibly connected to sinks) that can further crunch the RC network effectively after eliminating internal nodes [1,14]. Our method produces a realizable RC circuit and preserves the total capacitance in the network. While our technique cannot guarantee preserving the Elmore delay at each network sink node, the maximum delay error can be controlled by the user. Our method provides a smooth tradeoff between run time and delay accuracy, ranging from full retention of all resistors to complete elimination.


Archive | 1990

Method for evaluating the timing of digital machines with statistical variability in their delays

Wilm E. Donath; Robert B. Hitchcock; Jeffrey P. Soreff


Archive | 2002

Method for reducing RC parasitics in interconnect networks of an integrated circuit

Vasant B. Rao; Ravichander Ledalla; Jeffrey P. Soreff; Fred L. Yang


Archive | 2005

Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect

Vasant B. Rao; Cindy Washburn; Jun Zhou; Jeffrey P. Soreff; Patrick M. Williams; David J. Hathaway


Archive | 1999

Methods and apparatus for performing slew dependent signal bounding for signal timing analysis

Jin-Fuw Lee; Daniel L. Ostapko; Jeffrey P. Soreff; C. K. Wong


Archive | 2001

Reduced pessimism clock gating tests for a timing analysis tool

David J. Hathaway; Jeffrey P. Soreff; Neil R. Vanderschaaf; James D. Warnock


TAU | 1999

Einstlt: transistor level timing with einstimer

Vasant B. Rao; Jeffrey P. Soreff; Timothy B. Brodnax; Robert E. Mains


Archive | 2009

SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC TIMING ANALYSIS

Eric A. Foreman; Peter A. Habitz; David J. Hathaway; Jeffrey G. Hemmett; Kerim Kalafala; Jeffrey P. Soreff


Archive | 2006

Multiple mode approach to building static timing models for digital transistor circuits

Jeffrey P. Soreff; Philip George Shephard; Fred L. Yang; Vasant B. Rao


Archive | 2009

SYSTEM AND METHOD FOR DEVICE HISTORY BASED DELAY VARIATION ADJUSTMENT DURING STATIC TIMING ANALYSIS

Eric A. Foreman; Peter A. Habitz; David J. Hathaway; Jeffrey G. Hemmett; Kerim Kalafala; Jeffrey P. Soreff

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