James D. Warnock

The design and implementation of a first-generation CELL processor

A CELL processor is a multi-core chip consisting of a 64b power architecture processor, multiple streaming processors, a flexible IO interface, and a memory interface controller. This SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high-frequency clock-rate.

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor

This paper reviews the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends. This paper then describes the architecture, circuit design, and physical implementation of a first-generation Cell processor and the design techniques used to overcome the above challenges. A Cell processor consists of a 64-bit Power Architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multi-core SoC, implemented in 90-nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.

Physical design of a fourth-generation POWER GHz microprocessor

The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnect, and functions in systems at 1.1 GHz, and dissipates 115 W at 1.5 V.

The circuit and physical design of the POWER4 microprocessor

The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.

A variable-size shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS

A shallow trench isolation (STI) technology, RIE (reactive ion etching), CVD (chemical vapor deposition) oxide fill, and polarization are used to realize lithography-limited, submicron device and isolation dimensions. A novel boron diffusion technique is used for nMOSFET field doping, so that the parasitic sidewall inversion (leakage) problem is eliminated. It is shown that both the channel width bias and the narrow channel effect are greatly reduced in the STI technology. The diffused field also allows the boron doping to be self-aligned to the n-well with a single masking step in CMOS. STI is used in conjunction with a MINT (merged isolation and node trench) cell in 16-Mb DRAM (dynamic random access memory) technology.<<ETX>>

A VLSI-compatible high-speed silicon photodetector for optical data link applications

A novel silicon photodetector suitable for high-speed, low-voltage operation at 780- to 850-nm wavelengths is reported. It consists of an interdigitated p-i-n detector fabricated on a silicon-on-insulator (SOI) substrate by using a standard bipolar process. Biased at 3.5 V, this device attains a -3-dB bandwidth in excess of 1 GHz at /spl lambda/=840 nm. The dc responsivity measured at /spl lambda/=840 nm on nonoptimized structures ranges from 0.05 to 0.09 A/W, depending on the finger shadowing factor. A new approach for improving the responsivity is proposed and quantitatively analyzed. The fabricated devices exhibit extremely low dark currents, small capacitance, large dynamic range, and no evidence of low-frequency gain. The overall performance and process compatibility of these photodetectors make them viable candidates for the fabrication of silicon monolithic receivers for fiber-optic data links.

A room temperature 0.1 /spl mu/m CMOS on SOI

An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 /spl mu/m) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 /spl mu/m were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 /spl Aring/ effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C/sub L/=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained. >

A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)

A novel planarization technique for variable size and pattern factors is presented. It is demonstrated that by the combination of reactive ion etching (RIE) and chemical mechanical polish (CMP), the process window is improved to the extent that the planarization becomes a reality. This technique is applied in the shallow trench isolation process which is used in 16-Mb DRAM (dynamic RAM) technology to achieve 0.5- mu m isolation/device dimensions. By a proper combination of RIE and CMP processes, the fundamental problem of tolerance accumulation from deposition and etchback of large film thicknesses is avoided. Excellent planarization is achieved in different areas of the DRAM chip with varying isolation sizes and pattern factors, including deep trench integration. High gate oxide breakdown yield (comparable to LOCOS isolation), which is indicative of the planarization low defect density, is demonstrated.<<ETX>>

Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing

A novel method for obtaining ultra-thin, defect-free silicon on insulator (SOI) film is introduced. This technique uses epitaxial lateral overgrowth of Si (ELO) and chemical-mechanical polishing (CMP). SOI films with thicknesses of 100 nm were obtained. These films were used in fabrication and dual poly CMOS devices. The quality of the SOI film obtained is the same as that of bulk silicon, and the device characteristics are comparable with those of devices fabricated on bulk. A minimum geometry unloaded inverter ring oscillator on SOI film obtained by ELO and CMP showed a speed improvement of 3* over the bulk devices.<<ETX>>

Identification of perimeter depletion and emitter plug effects in deep-submicrometer, shallow-junction polysilicon emitter bipolar transistors

Two new types of narrow-emitter effects are identified in shallow and narrow-junction polysilicon emitter bipolar transistors. These effects result from a lower doping concentration close to the emitter perimeter of large devices (perimeter depletion effect) or in very-narrow-emitter devices where the polysilicon plugs up the emitter window (emitter plug effect). The consequence is a locally shallower emitter junction which causes a reduced collector current density and a nonideal base current due to a partial overlap of the emitter-base space-charge region with the poly/monosilicon interface. The nonuniform doping in the polysilicon is verified by energy-dispersive X-ray spectroscopy (EDX) measurements. Electrical measurements give a clear indication of the emitter plug effect for two different self-aligned transistor structures, and further evidence is given by a comparison of various poly emitter processes. >