Jelle Van Rethy

Carbon Nanotube Circuit Integration up to Sub-20 nm Channel Lengths

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.

Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs

Low-power applications, such as sensing, are becoming increasingly important and demanding in terms of minimizing energy consumption, driving the search for new and innovative interface architectures and technologies. Carbon nanotube FETs (CNFETs) are excellent candidates for further energy reduction, as CNFET-based digital circuits are projected to achieve an order of magnitude improvement in energy-delay product compared with silicon-CMOS at highly scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to imperfections and variations such as those induced by mispositioned and metallic CNTs. These substantial imperfections and variations have prevented the demonstration of complex CNFET circuits until now. This paper presents the first demonstration of a subsystem, which is a complete capacitive sensor interface circuit, implemented entirely using CNFETs that can be fabricated reproducibly in a VLSI-compatible fashion. This is made possible by: 1) a digitally oriented interface architecture and 2) the imperfection-immune design paradigm, which combines design and processing techniques to successfully overcome CNT imperfections and variations. In addition to electrical measurements, we demonstrate correct operation of our CNFET circuitry by interfacing it with a sensor used to control a handshaking robot.

Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS

An energy-efficient and supply- and temperature-resilient resistive sensor interface in 130-nm CMOS technology is presented. Traditionally resistive sensors are interfaced with a Wheatstone bridge and an amplitude-based analog-to-digital converter (ADC). However, both the unbalanced Wheatstone bridge and the ADC are highly affected by supply voltage variations, especially in smaller CMOS technologies with low supply voltages. As alternative to ratiometric measuring, this paper presents a force-balanced Wheatstone bridge interface circuit with a highly digital architecture that combines the advantage of energy-efficient sensing with highly improved overall PSRR and temperature resilience in one circuit. The prototyped circuit has a noise-frequency-independent PSRR of 52 dB, even for supply-noise amplitudes up to +10 dB FS. The maximum absolute output error in a supply voltage range of 0.85-1.15 V is only 0.7%, while the maximum absolute output error in a temperature range of 100°C is only 0.56% or 56 ppm/°C. The complete interface is prototyped in 130-nm CMOS and consumes 124.5 μW from a 1-V supply with a 10-kHz input bandwidth and 10.4-b resolution and 8.9-b linearity, resulting in a state-of-the-art sensor figure of merit of 13.03 pJ/bit-conversion.

Performance Analysis of Energy-Efficient BBPLL-Based Sensor-to-Digital Converters

Highly digital-oriented architectures for sensor interfaces are very interesting for their high energy efficiency, especially in smaller CMOS technologies which offer low-voltage design. This paper presents the analysis of a Bang-Bang Phase-Locked Loop Sensor-to-Digital Converter (BBPLL SDC). The highly digital-oriented BBPLL offers advantages such as the low chip area, excellent scalability towards smaller technologies, robustness towards process variations and low-voltage possibilities, making this architecture very interesting for energy-efficient applications. Theoretical analysis of the structure shows that the BBPLL SDC resembles a -modulator with first-order quantization noise shaping due to the frequency-to-phase conversion of the oscillators. Oscillator phase noise however plays an important role in the analysis and limits the SNR in practical implementations. To validate the theoretical analysis, a state-variable-based non-linear Matlab model has been developed, including non-idealities such as phase noise, non-linearity and mismatch. Based on practically achievable phase noise values of state of the art oscillators, simulations show that resolutions up to 110 dB can be achieved. An estimation of the power consumption of the oscillators, based on state of the art figures, results in energy-efficient designs beyond the state of the art with moderate resolutions of 40-80 dB SNR, while high resolutions of 80-110 dB demand higher power consumption in the oscillators, resulting in designs with lower energy efficiency, but still competitive with the current state of the art. A design strategy for both an energy-efficient and a high-performance BBPLL SDC is provided.

An energy-efficient capacitance-controlled oscillator-based sensor interface for MEMS sensors

This paper presents the optimization and implementation of an area- and energy-efficient capacitance-controlled oscillator-based sensor interface, which outputs a period-modulated signal. This time-based output signal can easily be digitized with a reset counter, which benefits from firstorder quantization noise shaping and oversampling. The circuit is prototyped in 130-nm CMOS technology and takes only 0.05 mm2. The performance is validated with both an external variable capacitor and a bare-die MEMS capacitive pressure sensor. The chip consumes 371 μW from a 1.2-V supply voltage and achieves 10.5-b resolution with 10-kHz input bandwidth for an input capacitance ranging from 3.7 to 13.7 pF. For both the external capacitor and the MEMS sensor, measurements show an improved energy efficiency compared to prior period modulation-based sensor interfaces.

Sacha: the Stanford carbon nanotube controlled handshaking robot

Low-power applications, such as sensing, are becoming increasingly important and demanding in terms of minimizing energy consumption, driving the search for new and innovative interface architectures and technologies. Carbon Nanotube FETs (CNFETs) are excellent candidates for further energy reduction, as CNFET-based digital circuits are projected to potentially achieve an order of magnitude improvement in energy-delay product at highly scaled technology nodes. This paper presents an overview of the first demonstration of a complete sub-system, a sensor interface circuit, implemented entirely using CNFETs. The demonstrated sub-system is an all-digital capacitive sensor to digital converter. The CNFET sensor interface is demonstrated by using the CNFET circuitry to interface with a sensor used to control a handshaking robot.

An energy-efficient BBPLL-based force-balanced Wheatstone bridge sensor-to-digital interface in 130nm CMOS

An energy-efficient time-based sensor interface in 130nm CMOS technology is presented for resistive sensors. Traditionally resistive sensors are interfaced with a voltage divider or a Wheatstone bridge to transform the sensor signal to a voltage. However, both the voltage divider and the unbalanced Wheatstone bridge are highly affected by supply voltage variations, especially in smaller CMOS technologies with low supply voltages. As alternative to ratiometric measuring, this paper presents a force-balanced Wheatstone bridge interface circuit with a highly digital architecture, that offers the advantage of low power consumption with highly improved overall PSRR. It has a noise-frequency-independent PSRR of 52dB for in-band supply noise and supply noise amplitudes up to +10dBFS, which is an improvement of 46dB over the voltage divider and of 26dB over the unbalanced Wheatstone bridge. Apart from the sensor calibration, no other calibration or absolute precise clock or voltage references are needed due to the BBPLL-based architecture. The complete interface consumes only 124.5μW from a 1V supply with 10kHz input bandwidth and 10.4 bit resolution and 8.9 bit linearity, resulting in a state-of-the-art sensor Figure of Merit of 13.03 pJ/conversion.

Predictive sensing in analog-to-digital converters for biomedical applications

This paper presents a predictive sensing-based ADC architecture that has improved energy efficiency, compared to a conventional SAR ADC, by exploiting the predictable properties of biomedical signals, such as the electrocardiogram (ECG) signal. By predicting the next input sample, based on previous samples, the conversion is performed in a subrange of the full scale. This results in energy savings compared to the SAR ADC, which always performs the conversion in the full scale. Two search algorithms to perform the conversion in the subrange will be presented and analyzed. For moderate resolutions between 6 and 10 bit, up to 40-50% improvement in terms of energy consumption is obtained, while 25 to 40% for higher resolutions. To validate the concept, a 12-bit predictive ADC, implementing the restricted binary search algorithm with 0-th order prediction, is designed and simulated in 130nm UMC CMOS technology. The simulation results show an improvement in the average energy consumption per conversion, compared to a conventional SAR ADC with the same resolution, which is in the range of 30-40%.

Time-based sensor interface circuits in carbon nanotube technology

Carbon nanotube technology is a promising technology to further reduce the energy consumption in electronics, as it is projected to achieve an order of magnitude improvement in energy-delay product compared to Silicon CMOS at highly-scaled technology nodes. In addition, CNTs are excellent candidates to be functionalized as sensors, and can potentially improve the energy efficiency of sensors and sensor interfaces for future autonomy-demanding applications. This paper presents an overview of time-based sensor interfaces implemented in a CNT technology. Time-based sensor interfaces yield highly-digital architectures, allowing for scalable and robust designs. All of the presented CNFET-based sensor interface circuits have been fabricated in a VLSI-compatible manner and have been validated through measurements.

Towards Energy-Efficient CMOS Integrated Sensor-to-Digital Interface Circuits

The ever increasing demand for improved autonomy in wireless sensor devices, drives the search for new energy-efficient sensor interface topologies in CMOS technology. Recently, time-based conversion has gained a lot of interest due to its high potential to implement highly-digital circuitry. While voltage-based analog integrated circuits suffer from the decreased supply voltage and voltage swing in highly-scaled CMOS technologies, time-based processing takes advantage of the increased timing resolution. However, how do these time-based sensor interface circuits compare to their amplitude-based counterparts fundamentally? To answer this question, theoretical limits are derived in this chapter for both implementations, which shows that the sensor itself is actually the dominant factor in limiting the achievable energy efficiency. Time-based topologies, however, enable the implementation of highly-digital interfaces, which are scalable, area-efficient and have low-voltage potential. These observations are illustrated with several practical designs.