Georges Gielen

Computer-aided design of analog and mixed-signal integrated circuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

Symbolic Analysis for Automated Design of Analog Integrated Circuits

1. Introduction to Analog Design Automation.- 1.1. Introduction.- 1.2. Definitions in analog design automation.- 1.3. Characteristics of analog design.- 1.4. Needs for analog circuits and analog design automation.- 1.5. Different analog design approaches and analog silicon compilation.- 1.6. Analog system-level synthesis.- 1.7. Outline of the book.- 2. The Automated Design of Analog Functional Modules.- 2.1. Introduction.- 2.2. Classification of analog module design programs.- 2.3. An automated design methodology for analog modules.- 2.4. The methodology applied to a simple example.- 2.5. Discussion of and comparison with other analog design systems.- 2.6. Conclusions.- 3. Symbolic Simulation of Analog Integrated Circuits.- 3.1. Introduction.- 3.2. Definition and scope of symbolic simulation.- 3.3. Applications of symbolic analysis in analog design.- 3.4. General description of the ISAAC program.- 3.5. Conclusions.- 4. Algorithmic Aspects of Linear Symbolic Simulation.- 4.1. Introduction.- 4.2. Overview of symbolic analysis techniques.- 4.3. The set-up of the linear circuit equations.- 4.4. The symbolic solution of sets of linear equations.- 4.5. Symbolic expression approximation.- 4.6. Performance of the ISAAC program.- 4.7. Conclusions.- 5. Symbolic Distortion Analysis.- 5.1. Introduction.- 5.2. Symbolic noise analysis.- 5.3. Symbolic analysis of harmonic distortion in weakly nonlinear analog circuits.- 5.4. Symbolic sensitivity analysis and zero/pole extraction.- 5.5. Techniques for the hierarchical symbolic analysis of large circuits.- 5.6. Conclusions.- 6. Analog Design Optimization Based on Analytic Models.- 6.1. Introduction.- 6.2. Circuit sizing based on an optimization of analytic models.- 6.3. The analog design formulation in OPTIMAN.- 6.4. Practical design examples.- 6.5. Automated layout generation of analog integrated circuits.- 6.6. Conclusions.- Appendix A. Characterization of a CMOS Two-Stage OPAMP.- References.

A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC

In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q/sup 2/ random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-/spl mu/m CMOS process. The die area is 13.1 mm/sup 2/.

ISAAC: a symbolic simulator for analog integrated circuits

The symbolic simulator ISAAC (interactive symbolic analysis of analog circuits) is presented. The program derives all AC characteristics for any analog integrated circuit (time-continuous and switched-capacitor, CMOS, JFET, and bipolar) as symbolic expressions in the circuit parameters. This yields analytic formulas for transfer functions, CMRR (common-mode rejection ratio), PSRR (power-supply rejection ratio), impedances, noise, etc. Two novel features are included in the program. First, the expressions can be simplified with a heuristic criterion based on the magnitudes of the elements. This yields interpretable formulas showing only the dominant terms. Second, the explicit representation of mismatch terms allows the accurate calculation of second-order effects, such as the PSRR. ISAAC provides analog designers with more insight into the circuit behavior than do numerical simulators and is a useful tool for instruction or designer assistance. Moreover, it generates complete analytic AC circuit models, which are used for automatic sizing in a nonfixed topology analog module generator. The programs capabilities are illustrated with several examples. The efficiency is established by a dedicated sparse-matrix algorithm. >

Symbolic analysis methods and applications for analog circuits: a tutorial overview

This tutorial paper gives an overview of the history and present state of the art in symbolic analysis of electronic circuits at the so-called circuit level. Symbolic analysis is defined as a technique generating a closed-form analytic expression for a circuit characteristic with the circuits elements represented by symbols. Such analytic information complements the results from numerical simulations. The paper then describes the different application areas of symbolic analysis for the design of analog circuits. Symbolic analysis is mainly used as a means to obtain insight into a circuits behavior, to generate analytic models for automated circuit sizing, and in applications requiring the repetitive evaluation of circuit characteristics. Next, the present capabilities and limitations of symbolic analysis, both in functionality and efficiency, are discussed. The major symbolic analysis methods are presented, and algorithmic details are provided for symbolic approximation, hierarchical decomposition, and symbolic distortion analysis. Finally, existing symbolic simulators are compared, and directions for future research are pointed out. >

WATSON: design space boundary exploration and model generation for analog and RFIC design

A new method is described which gives the designer access to the design space boundaries of a circuit topology, all with transistor-level accuracy. Using multiobjective genetic optimization, the hypersurface of Pareto-optimal design points is calculated. Tradeoff analysis of competing performances at the design space boundaries is made possible by the application of multivariate regression techniques. This new methodology is illustrated with the presentation of the design space for two different types of circuits: a Miller-compensated operational transconductance amplifier and an LC-tank voltage-controlled oscillator.

AMGIE-A synthesis environment for CMOS analog integrated circuits

A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the systems database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

A performance-driven placement tool for analog integrated circuits

This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designers specifications. This guarantees that the resulting layout will meet all specifications by construction. During each iteration of the simulated annealing algorithm, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool inherently handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples. >

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

More and more system-on-chip designs require the integration of analog circuits on large digital chips and therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on the analog circuits, information is needed about digital substrate noise generation. A methodology for modelling and simulating the time-domain waveform of the generated substrate noise of large digital circuits is verified with measurements on an 86k-gate CMOS ASIC. The difference between simulated and measured substrate noise RMS voltage is <10% and simulation time is of the same order of magnitude as a gate-level VHDL simulation. For smaller circuits, e.g., a 1k-gate multiplier, a speedup in simulation time of 3 orders of magnitude is obtained with respect to a full SPICE simulation.

An implantable 455-active-electrode 52-channel CMOS neural probe

Several studies have demonstrated that understanding certain brain functions can only be achieved by simultaneously monitoring the electrical activity of many individual neurons in multiple brain areas [1]. Therefore, the main tradeoff in neural probe design is between minimizing the probe dimensions and achieving high spatial resolution using large arrays of small recording sites. Current state-of-the-art solutions are limited in the amount of simultaneous readout channels [2], contain a small number of electrodes [2,3] or use hybrid implementations to increase the number of readout channels [3,4].