Hans Danneels

A fully-digital, 0.3V, 270 nW capacitive sensor interface without external references

This paper presents a fully-digital capacitive sensor interface. By directly transforming the sensor value instead of using an intermediate step in the voltage domain, the architecture can cope with very low signal swings. An implementation for barometric pressure sensing with a supply voltage of 0.3 V demonstrates the benefits. With a power consumption of only 270 nW and an acquisition time of 1 ms, an ENOB of 6.1 is obtained, resulting in a FOM of 2.1 pJ/conv for the entire interface. This is at least an order of magnitude better than current state-of-the-art implementations.

Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS

An energy-efficient and supply- and temperature-resilient resistive sensor interface in 130-nm CMOS technology is presented. Traditionally resistive sensors are interfaced with a Wheatstone bridge and an amplitude-based analog-to-digital converter (ADC). However, both the unbalanced Wheatstone bridge and the ADC are highly affected by supply voltage variations, especially in smaller CMOS technologies with low supply voltages. As alternative to ratiometric measuring, this paper presents a force-balanced Wheatstone bridge interface circuit with a highly digital architecture that combines the advantage of energy-efficient sensing with highly improved overall PSRR and temperature resilience in one circuit. The prototyped circuit has a noise-frequency-independent PSRR of 52 dB, even for supply-noise amplitudes up to +10 dB FS. The maximum absolute output error in a supply voltage range of 0.85-1.15 V is only 0.7%, while the maximum absolute output error in a temperature range of 100°C is only 0.56% or 56 ppm/°C. The complete interface is prototyped in 130-nm CMOS and consumes 124.5 μW from a 1-V supply with a 10-kHz input bandwidth and 10.4-b resolution and 8.9-b linearity, resulting in a state-of-the-art sensor figure of merit of 13.03 pJ/bit-conversion.

Performance Analysis of Energy-Efficient BBPLL-Based Sensor-to-Digital Converters

Highly digital-oriented architectures for sensor interfaces are very interesting for their high energy efficiency, especially in smaller CMOS technologies which offer low-voltage design. This paper presents the analysis of a Bang-Bang Phase-Locked Loop Sensor-to-Digital Converter (BBPLL SDC). The highly digital-oriented BBPLL offers advantages such as the low chip area, excellent scalability towards smaller technologies, robustness towards process variations and low-voltage possibilities, making this architecture very interesting for energy-efficient applications. Theoretical analysis of the structure shows that the BBPLL SDC resembles a -modulator with first-order quantization noise shaping due to the frequency-to-phase conversion of the oscillators. Oscillator phase noise however plays an important role in the analysis and limits the SNR in practical implementations. To validate the theoretical analysis, a state-variable-based non-linear Matlab model has been developed, including non-idealities such as phase noise, non-linearity and mismatch. Based on practically achievable phase noise values of state of the art oscillators, simulations show that resolutions up to 110 dB can be achieved. An estimation of the power consumption of the oscillators, based on state of the art figures, results in energy-efficient designs beyond the state of the art with moderate resolutions of 40-80 dB SNR, while high resolutions of 80-110 dB demand higher power consumption in the oscillators, resulting in designs with lower energy efficiency, but still competitive with the current state of the art. A design strategy for both an energy-efficient and a high-performance BBPLL SDC is provided.

RFID, where are they?

This paper gives an overview of RFID technology. RFID systems are described in general and a few example cases are given. After that the paper mainly focuses on the hardware requirements for RFIDs. Also Real Time Locationing Systems (RTLS) are discussed. This gives the title of the paper a double meaning: ‘what is the state of the art in RFID’ but also what is the available technology to come to locationing capable RFID systems. The paper gives an overview of the design challenges of different RFID systems. Also possible circuit solutions and directions are addressed.

A 0.5 V-1.4 V supply-independent frequency-based analog-to-digital converter with fast start-up time for wireless sensor networks

RF-powered wireless sensor networks demand for ultra-low-energy A/D converters. Such systems have specific requirements, like fast start-up time and supply voltage independence. The presented A/D converter is based on a digital phase locked loop. Two closely matched ring oscillators perform the analog to frequency conversion. The digital output is generated by an in-loop digital proportional-integral filter. The acquisition of the PLL is splitted into coarse and fine tuning to reduce the locking time to less than 30µs. A UMC130 CMOS technology is used to simulate a temperature sensor interface. The energy consumption is maximally 212 pJ per conversion and the effective number of bits is 7 bit in a 0.5 V-1.4 V supply voltage range.

An energy-efficient BBPLL-based force-balanced Wheatstone bridge sensor-to-digital interface in 130nm CMOS

An energy-efficient time-based sensor interface in 130nm CMOS technology is presented for resistive sensors. Traditionally resistive sensors are interfaced with a voltage divider or a Wheatstone bridge to transform the sensor signal to a voltage. However, both the voltage divider and the unbalanced Wheatstone bridge are highly affected by supply voltage variations, especially in smaller CMOS technologies with low supply voltages. As alternative to ratiometric measuring, this paper presents a force-balanced Wheatstone bridge interface circuit with a highly digital architecture, that offers the advantage of low power consumption with highly improved overall PSRR. It has a noise-frequency-independent PSRR of 52dB for in-band supply noise and supply noise amplitudes up to +10dBFS, which is an improvement of 46dB over the voltage divider and of 26dB over the unbalanced Wheatstone bridge. Apart from the sensor calibration, no other calibration or absolute precise clock or voltage references are needed due to the BBPLL-based architecture. The complete interface consumes only 124.5μW from a 1V supply with 10kHz input bandwidth and 10.4 bit resolution and 8.9 bit linearity, resulting in a state-of-the-art sensor Figure of Merit of 13.03 pJ/conversion.

A low-power mixing DAC IR-UWB-receiver

This paper introduces a novel receiver architecture for low-power IR-UWB receivers in the 3.75-4.25 GHz band. The receiver correlates the incoming pulse with an approximated pulse template in the analog domain. The template is learnt digitally and transferred to the analog domain via a low resolution DAC. The paper presents the design of the mixing DAC that implements the downconverter, DAC and correlator which consumes only 875 uW in 90 nm CMOS technology. The DAC receiver topology requires 4 dB less energy per incoming bit in comparison with current state-of-the-art IR-UWB receivers.

Scalable Bang-Bang Phase-Locked-Loop-based integrated sensor interfaces

The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang-Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect.

A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks

A low-power and low-voltage BBPLL-based sensor interface for resistive sensors in Wireless Sensor Networks is presented. The interface is optimized towards low power, fast start-up time and fast conversion time, making it primarily useful in autonomous wireless sensor networks. The interface is time/frequency-based, making it less sensitive to lower supply voltages and other analog non-idealities, whereas conventional amplitude-based interfaces do suffer largely from these non-idealities, especially in smaller CMOS technologies. The sensor-to-digital conversion is based on the locking behavior of a digital PLL, which also includes transient behavior after start-up. Several techniques such as VDD scaling, coarse and fine tuning and pulse-width modulated feedback are implemented to decrease the transient and acquisition time and the power to optimize the total energy consumption. In this way the sensor interface consumes only 61µW from a 0.8V DC power supply with a one-sample conversion time of less than 20µs worst-case. The sensor interface is designed and implemented in UMC130 CMOS technology and outputs 8 bit parallel with 7.72 ENOB. Due to its fast start-up time, fast conversion time and low power consumption, it only consumes 5.79 pJ/bit-conversion, which is a state-of-the-art energy efficiency compared to recent resistive sensor interfaces.

RFID, Where are they?

This paper gives an overview of RFID technology. RFID systems are described in general and a few example cases are given. After that the paper mainly focuses on the hardware requirements for RFIDs. Also Real Time Locationing Systems (RTLS) are discussed. This gives the title of the paper a double meaning: ‘what is the state of the art in RFID’ but also what is the available technology to come to locationing capable RFID systems. The paper gives an overview of the design challenges of different RFID systems. Also possible circuit solutions and directions are addressed.