Jen-Chieh Lin

Process development of replacement metal gate Tungsten chemical mechanical polishing on 14nm technology node and beyond

The control of gate height uniformity, especially within-die gate height uniformity, and metal gate surface properties of 14nm technology node replacement metal gate (RMG) chemical mechanical polishing is important for 14nm high-k metal gate (HKMG) process. Good within-die uniformity would benefit for the following Tungsten etching back process(WEB) to have a uniform within-die etching depth, and proper post CMP Tungsten gate surface properties would generate a thinner Tungsten oxide surface to reduce WEB process loading. This study demonstrated the possibility of Tungsten gate CMP(WGCMP) to obtain good within-die gate height uniformity by selection of slurry and proper Tungsten gate surface by post buffing step CMP treatment. Due to high hardness of Tungsten, hardness of polishing pad and abrasive of slurry selection should be not a gap for micro scratch improvement, what the performance focus would put on within-die uniformity and post CMP Tungsten surface properties. In this study, the first result showed the control of erosion was important for within-die gate height uniformity. The criteria of slurry selection for WGCMP were higher Tungsten removal rate and lower oxide removal rate which especially resulted in lower pattern density area of erosion. And the second result showed Chemical-A polish time of post-Tungsten buffing CMP would dominate the Tungsten surface properties and influence WEB behavior.

The L28 STI CMP Dummy Pattern Study on Topography for Advanced Fixed Abrasive and High Selective Slurry

Since the sub-0.25 μm technology node, the shallow trench isolation (STI) was the process of choice to replace local oxidation of silicon (LOCOS) for the transistors of complimentary metal oxide semiconductor (CMOS) devices [1, 2]. The STI CMP performance was major determined by the uniformity of STI step height which was characterized by the ranges of within-die (WID) and within-wafer (WIW) thickness for both silicon nitride and trench oxide surface of isolation area [3]. Currently, for 28nm generation, two advanced approaches for STI CMP were high selective slurry (HSS) and fixed abrasive (FA) CMP. For these two approaches, the design and layout of dummy were important to overcome the effect of various pattern densities and feature sizes. For this reason, this research studied and compared the effect of dummy on the two different STI CMP processes and found a better way to meet the STI step height range control for 28 nm node and beyond. In this research, L28 logic pattern wafers with two different STI test keys were prepared and filled with subatmospheric chemical vapor deposition (SACVD) dielectric oxide film. Both HSS and FA STI CMP were executed for the comparison. Specific testkey sets were designed for the dummy effect study. Every testkey set have different pattern density (PD) varied from 10% to 90%. 5 testkey sets were surrounded with 5 various dummies, as showed in Table 1, independently. This research focused on the effect of dummy type for HSS and FA STI CMP. Figure 1 and 2 show the dummy effect on nitride thickness of test keys across different pattern density after HSS and FA CMP process, respectively. The pattern density of dummy shows an important effect on FA CMP. The dummy 1 which has the lowest pattern density in theses five dummies shows the worst non-uniformity of nitride thickness, which decreases as pattern density of test key lower than 70 %, after FA CMP process. On the contrary, the HSS CMP shows weak dependence on the pattern density of dummy. This result shows HSS CMP is relative insensitive to the PD of both dummy and test pattern. It is preferred for STI CMP process. On the other hand, for FA CMP, choosing proper dummy pattern is important to sustain the better non-uniformity of nitride thickness across wide PD range. In addition, this research also studied the dummy effect on trench oxide dishing, as shown in Figure 3. For HSS CMP, dishing amount is not sensitive to dummy pattern through it is higher than FA CMP process no matter the dummy type is. FA CMP process performs less dishing extent than HSS CMP process, especially in Dummy 4 and Dummy 5. It means that dummy with high pattern density and small spacing benefits to dishing performance at FA CMP. The result shows dummy layout is important for STICMP process. In this research, the dummy with higher pattern density shows better performance at nitride thickness uniformity and trench oxide dishing. Nevertheless, the CMP process is the most important factor for STICMP. The HSS CMP process has better performance at nitride thickness uniformity and is not affected by the layout of dummy.

Evaluation of aluminum film properties and microstructure for replacement metal gate application at 28nm technology node

The fundamental film properties and microstructures of the different aluminum (Al) metal layers are evaluated to fabricate a replacement metal gate (RMG) device for the high-k metal gate (HKMG) application at 28nm node. A PVD Al fill-in metal deposition process, called one step hot Al (HAL), was found the resistivity increases with increasing the thickness of the Ti wetting layer. The higher pinhole density with the preferred (111) crystal orientation in the HAL layers indicate the film properties with lower reflectivity, higher resistivity and lower removal rate of the Al chemical mechanical polishing (AlCMP). In contrast, the other PVD Al deposition approach, called two steps cold hot Al (CHAL), was identified to possess lower resistivity and higher reflectivity without pinhole structures than the HAL. The smaller grain sizes with the preferred (220) orientation in the CHAL could effectively prevent the formation of pinhole and enhance the removal rate of the AlCMP. The non-uniform with crystallized TiAl3 phase detected in the bottom of the as-deposited HAL and CHAL films could obviously impact the removal rate of the AlCMP. An optimized CHAL fill-in metal deposition process with a larger than 40Å Ti wetting layer are needed to simultaneously meet the process requirements of the Al gapfill and AlCMP planarization for achieving a reliable RMG structures.

Integrated NiSi defect reductions in 45nm node and beyond

Nickel silicide has been popular used for source/drain (S/D) contact materials in 45nm node and beyond in complementary metal-oxide semiconductor device because of its low silicon consumption and low sheet resistance loading among variant line widths, but the drawback is poor thermal stability [1–2] which is easy to worsen pre-layer damage and induce leakage defects like piping, agglomeration. So some approaches like impurity engineering with fluorine and Pt additive for improving NiSi thermal stability, and annealing time and temperature optimization for gain and roughness improvement. Additionally, some thermal techniques for end-of-line (EOR) defect recovery were addressed to reduce leakage defects. This study successfully demonstrates three orders defect reduction by integrating them.

Advanced Rework Process Development for Cu-CMP at 28 nm Technology Node

As IC fabrication scales down, RC delay time concern brings Cu used instead of Al as interconnects. Owing to difficult plasma etching for Cu removal, Cu metallization nowadays has been carried out with damascene process. After that, Cu chemical mechanical polishing (Cu-CMP) technology plays an important role to achieve excellent Cu planarization for IC fabrication [1]. However, the Cu thickness post CMP is critical to Cu resistance as a function of RC delay time. Advance CuCMP should require excellent control to Cu remaining thickness post CMP. Unfortunately, there is no effective end-point detection technique nowadays to stop barrier removal step in conventional Cu-CMP process. Frequent re-work (RW) process post Cu-CMP is inevitable to address ideal Cu thickness [2]. Nevertheless, currently Cu-CMP RW process could result in worse uniformity of electric properties as compared with no RW condition (Figure 1). This investigation tries to eliminate the variation of Cu line sheet resistance (Rs) after implementing an optimum Cu-CMP RW polishing condition. 300mm blanket wafers with Cu and ultra-low k (ULK, k~2.5) films were prepared to characterize the removal rates and the selectivity of Cu to ULK film for different slurry flow rate, polishing down force and platen speed test conditions. The thickness for Cu and ULK film were estimated by means of n & k measurement. 28nm pattern wafers with Cu/ULK dual damascene structure were used for electric properties measurement and TEM check in Cu line. All polishing processes were carried out on an orbital type polisher with silica-based slurry. Figure 2 shows the Rs variation of Cu line increases more 65% higher than no RW condition as using original Cu-CMP polishing condition (split 1) for RW process at 28nm product. On the contrary, the split 3 RW condition can obtain the comparable Rs variation level as compared with no RW process. The similar benefit of this optimum RW process also can be demonstrated at 40nm FPGA product, as shown in Figure 3(a)-(b). Figure 4 indicates the removal rates of Cu and ULK films increase and the selectivity of ULK to Cu film decreases with increasing split condition number. Split 3 shows the highest removal rates of Cu and ULK films and lower selectivity of ULK to Cu film in comparison to split 1 and split 2. Higher removal rate of Cu film during RW is benefit to reduce total RW polishing time. Longer Cu-CMP RW time is well known to impact the uniformity control of Cu line thickness. On the other hand, the selectivity of ULK to Cu changes to be lower from split 1 to split3 test condition. The split 3 condition shows the largest removal rate gap between Cu and ULK film. In comparison with the removal rate of Cu film, lower removal rate of ULK film is also helpful to compensate the Cu line morphology from original no RW condition with lightly protrusion profile to optimum RW condition with flat profile, as shown in Figure 5(a)-(b). An optimum RW condition with higher removal rate of Cu film and lower selectivity of ULK to Cu film has been demonstrated can eliminate the variation of Cu line sheet resistance (Rs) as compared with no RW polishing condition. References