J. Y. Wu

A comparative study of gate stack material properties and reliability characterization in MOS transistors with optimal ALD Zirconia addition for hafina gate dielectric

In this work, we investigate the influence of incorporation Zirconia (ZrO₂) in gate dielectric HfO₂ on electrical properties and the reliability of nMOSFET for the 28nm technology node. Detailed film physical, chemical and optical properties of Hf_1-xZr_xO₂ as a function of Zr content were studied using HRTEM, AR-XPS, spectroscopic ellipsometer. Compared to HfO₂, Hf_1-xZr_xO₂ provides lower C-V hysteresis, V_t shift (ΔV_t) and higher Time to Failure (TTF) lifetimes are achieved with Zr incorporation in an ALD Hf_1-xZr_xO₂/SiO2 gate stack. The improved reliability of the Hf_1-xZr_xO₂ gate dielectric is attributed to the reduced charge trapping in the Hf_1-xZr_xO₂ gate dielectric caused by the Zr incorporation.

A comprehensive process engineering on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40nm technology node and beyond

The failure ratios of the three typical time-dependent dielectric breakdown (TDDB) failure modes, including top interface, sidewall and bottom corner areas, have been identified for a direct polishing ultra low k (ULK) dielectric Cu back-end-of-line (BEOL) structure at 40nm node. The Cu surface roughness of the metal lines, and the adhesion and thickness of the metal capping layers are strongly correlated to the top interface failure mode. The dielectric constant of the ULK and the concentration of the aluminum-doped Cu (CuAl) seed layer could be related to the sidewall failure mode. The bottom corner failures are induced by inappropriate Cu barrier re-sputter processes. In this study, the TDDB reliability performance can be effectively improved by evaluating a post-Cu chemical mechanical polishing (Cu CMP) cleaning process with smooth Cu surface roughness, developing a better step coverage with multi-layer capping layer, using a slightly higher dielectric constant ULK film, replacing a conventional pure Cu with a CuAl seed layer and optimizing the Cu barrier layer deposition process. The lifetime of the TDDB can be significantly improved over three orders (larger than 10000 years) as implementing an optimized integrated Cu with ULK BEOL structures at 40nm technology node.

The investigation of galvanic corrosion in post-copper-CMP cleaning

The characteristics of galvanic corrosion in post-copper CMP cleaning are investigated. This type of corrosion occurs when CMP process completed, due to the heating lamp in SRD step. Particularly, it occurs only in device wafer, but not in structural test wafer. The corrosion behavior with light was identified. It occurs not only in integrated cleaner, but also in stand alone brush type cleaner. Copper lines were bridged after corrosion. The corrosion by-product can be removed by means of solvent cleaning. The mechanism and the prevention of this type of light-induced corrosion are reported in this paper.

The investigation of electroplating deposited copper films for advanced VLSI interconnection

The characteristics of electroplating deposited (EPD) copper films after annealing are investigated by means of sheet resistance, film hardness, film stress, surface roughness, and the chemical mechanical polishing process. Films annealed at 150/spl deg/C showed very similar behavior to those annealed at room temperature for three days in many aspects, including sheet resistance, hardness, surface morphology, and CMP polish rate. Annealing at temperatures higher than 300/spl deg/C resulted in lower sheet resistance, larger grain size, and rougher surfaces, as well as better CMP performance. Atomic force microscopy showed that the surface was rougher as the annealing temperature increased. Better CMP polish rate and uniformity were obtained on fully recrystallized films. Therefore, post-EPD annealing at about 300/spl deg/C to stabilize the copper films is necessary for better CMP process performance.

Extremely low power c-axis aligned crystalline In-Ga-Zn-O 60 nm transistor integrated with industry 65 nm Si MOSFET for IoT normally-off CPU application

For the first time, laboratory 60 nm c-axis aligned crystalline In-Ga-Zn-O (CAAC-IGZO) oxide semiconductor FET (OSFET) was successfully integrated with industrial 65 nm Si MOSFET (SiFET). By this hybrid process, OSFET with extremely low off-state leakage level ~zA (1×10-21A) was fabricated, while traditional Si device can only reach 1×10-12A leakage level. For IoT (Internet of Things) applications, normally-off CPU (Noff CPU) fabricated by this hybrid process achieved 86% reduction of power consumption. The hybrid process can be extended to other applications like eDRAM, image sensor and FPGA.

Effects of BEOL copper CMP process on TDDB for direct polishing ultra-low k dielectric cu interconnects at 28nm technology node and beyond

A robust Cu chemical mechanical polishing (CMP) process with better post CMP polishing profile, range, lower defectivity, smooth copper surface, tighten metal line sheet resistance (Rs) and pattern loading control has been evaluated during the Cu-CMP process at 28nm and beyond. Various reasons of Time-Dependent Dielectric Breakdown (TDDB) failure including micro-scratches on interconnect surface post Cu CMP, new barrier slurry with lower solid content, smaller abrasive size and polish pad with lower hardness than Dow pad IC pad from a direct polishing ultra low k (ULK) dielectric Cu back-end-of-line (BEOL) structure at 28nm node and beyond will be discussed. It is clearly shown that with smaller slurry abrasive and lower content ratio, TDDB performance can be improved. Furthermore, based on this study, the TDDB reliability performance also can be effectively improved by using a new barrier slurry with better copper recess and pattern density loading control, soft polish pad with smooth Cu surface, a better step coverage with multi-layer capping layer, and a slightly higher dielectric constant ULK film. The lifetime of the TDDB can be significantly improved over two orders of magnitudes by implementing an optimized new barrier slurry and softer polish pad at 28nm technology node.

Defect reduction of copper BEOL for advanced ULSI interconnect

In this paper, a full discussion of the defect reduction in copper BEOL technology of a 1P/3M logic product is presented for the first time. Defectivity is inspected from AEI to CMP on various metal levels. Defectivity is classified into non CMP-related type and CMP-related type. Most of the non-CMP type defects are foreign matter coming from the environment or from the processing residues. They can be effectively removed in a CMP step, as long as they were not trapped in the metal trench. On the other hand, the CMP-related type defects impact the consecutive process and yield significantly. Examples of the killer defects are slurry residues, corrosion, and scratching. Prevention and reduction of defects is discussed. Product yield is greatly improved after the reduction of defectivity.

Fast and accurate scatterometry metrology method for STI CMP step height process evaluation

At the 28nm node using 300mm wafers, oxide step height in STI CMP transient gate after-etch inspection (TG AEI) wafers is a critical parameter that affects device performance and should be monitored and controlled. For production process control of this kind of structure, a metrology tool must utilize a non-destructive measurement technique, and have high sensitivity, precision and throughput [1]. This paper discusses a scatterometry-based measurement method for monitoring critical dimension step height in STI CMP instead of traditional measurement methods such as atomic force microscopy (AFM). The scatterometry tool we used for our investigations was the KLA-Tencor SpectraShape 8810, which is the most recent model of the spectroscopic critical dimension (SCD) metrology tools that have been implemented in production for process control of TG AEI structures. AFM was used as a reference metrology technique to assess the accuracy performance of the SpectraShape8810. The first objective of this paper is to discuss the best azimuth angle and floating parameters for scatterometry measurement of the step height feature in TG AEI wafers. Second, this paper describes the tool matching performance of SpectraShape 8810 and correlation to AFM determined using a DOE of TG AEI wafers.

Investigation of the structural and electrical characterization on ZrO 2 addition for ALD HfO 2 with La 2 O 3 capping layer integrated metal-oxide semiconductor capacitors

In this work, we report on ZrO<inf>2</inf> position effect of ALD HfZrO<inf>x</inf> gate dielectric with a La<inf>2</inf>O<inf>3</inf> capping layer for gate-first flow. The basic electrical characteristics of devices were compared with different ZrO<inf>2</inf> position in HfZrO<inf>x</inf> dielectric. Experimental results show : (1) Under top La<inf>2</inf>O<inf>3</inf> capping layer for n-type Metal-Oxide-Silicon capacitor (nMOSCAP) device, ZrO<inf>2</inf> position on both of top and bottom in HfZrO<inf>x</inf> shows higher leakage (>x5) current and V<inf>fb</inf> shift (−0.18V) to band edge than HfO<inf>2</inf> dielectric. (2) For the top La<inf>2</inf>O<inf>3</inf> cap device, ZrO<inf>2</inf> addition into ALD HfO<inf>2</inf> can have significant shift on J<inf>g</inf> and V<inf>fb</inf>. Bottom La<inf>2</inf>O<inf>3</inf> capping position stack has higher J<inf>g</inf> (>x4) and larger V<inf>fb</inf> shift (−0.15V) than the top La<inf>2</inf>O<inf>3</inf> cap position for nMOSCAP device.

The TDDB failure mode and its engineering study for 45nm and beyond in porous low k dielectrics direct polish scheme

To keep pursuing the chip resistance capacitance (RC) delay improvement, it is necessary to further reduce k value. Accordingly, direct polished porous type ultra-low-k (ULK) film instead of non-porous low-k materials is integrated into Cu interconnects from 45 nm. However, because of the ULK characteristics and the minimized feature size, the time-to-break-down (TDDB) failure mode behaves different from silica glass or nonporous low-k film. And it is not only sensitive to geometries but also very sensitive to the engineering in the fabrication process. In this paper, we identified three TDDB failure modes, Cu protrusion from trench top interface, sidewall, and bottom corner, in the direct polished ULK scheme. In addition, on the basis of those failure modes, the related mechanisms in conjunction with the sensitivity to the processes are reported as well.