Jengyi Yu

Predicting synergy in atomic layer etching

Atomic layer etching (ALE) is a multistep process used today in manufacturing for removing ultrathin layers of material. In this article, the authors report on ALE of Si, Ge, C, W, GaN, and SiO2 using a directional (anisotropic) plasma-enhanced approach. The authors analyze these systems by defining an “ALE synergy” parameter which quantifies the degree to which a process approaches the ideal ALE regime. This parameter is inspired by the ion-neutral synergy concept introduced in the 1979 paper by Coburn and Winters [J. Appl. Phys. 50, 5 (1979)]. ALE synergy is related to the energetics of underlying surface interactions and is understood in terms of energy criteria for the energy barriers involved in the reactions. Synergistic behavior is observed for all of the systems studied, with each exhibiting behavior unique to the reactant–material combination. By systematically studying atomic layer etching of a group of materials, the authors show that ALE synergy scales with the surface binding energy of the bu...

Advanced metallization scheme for 3×50µm via middle TSV and beyond

An advanced Via-Middle TSV metallization scheme is presented, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling process. Because of the high conformality of the WN barrier and NiB seed, these layers can be deposited very thinly, reducing the cost significantly, while still guaranteeing continuous barrier/seed layers all along the TSV sidewall till the bottom of the TSV. This metallization scheme has been successfully processed on 3 m diameter and 50 m deep Via-Middle TSVs, showing void-free copper fill in FIB cross-sections. Good adhesion between liner, barrier and seed was maintained during the processing, including the post plate anneal which is present to reduce the copper pumping. The polishing of the NiB seed and WN barrier has been optimized in order to limit the recess of these layers at the top of the TSV. Electrical results are shown, proving the maturity of this new TSV middle process scheme. Low leakage current in both accumulation and depletion mode is measured. The flat band voltage is low as well, indicating little ionic contamination in the liner oxide. The intrinsic integrity of the liner and the ability of the barrier to prevent Cu diffusion from TSV to silicon has been verified, using the established controlled I-V method. High field acceleration factors are extracted, ensuring good reliability of this advanced and scalable 3×50 TSV middle module.

Advanced integrated metallization enables 3D-IC TSV scaling

Innovative solutions have been developed to address the challenges of through-silicon via (TSV) metallization with small sizes and high aspect ratios. We demonstrate an advanced metallization scheme including conformal film depositions of metal barrier and seed with excellent sidewall coverage to achieve void-free Cu fill in small-size (10 to 1 μm) TSV with high aspect ratio (10:1 to 20:1). In addition, it reduces the field metal thickness to significantly lower the costs of metallization and subsequent CMP. TSVs fabricated using this new process integration scheme exhibited higher breakdown voltage and lower leakage current than those made with the conventional PVD barrier seed. No degradation in performance was observed after 400°C annealing and thermal cycling. The improved performance is attributed to the formation of pinhole-free metal barrier layer with excellent sidewall coverage.

Integrated approach to improving local CD uniformity in EUV patterning

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

Reliability study of liner/barrier/seed options for via-middle TSV's with 3 micron diameter and below

In high aspect ratio TSVs, the step coverage (conformality) of liner, barrier and seed is critical for both the integration and reliability. If the conformality of a deposition technique is improved, the required thickness to be deposited on the field of the wafer can be reduced. Consequently, less material needs to be removed by CMP on the field, which reduces the manufacturing cost. In this paper, the reliability of two liner/barrier/seed options, which were successfully integrated into via-middle TSVs with a diameter of 3 micron and an aspect ratio (AR) of 17 is investigated. Both controlled ramp rates (IVctri) as well as standard Time Dependent Dielectric Breakdown (TDDB) at 100°C were employed as electrical testing methods to investigate the dielectric and barrier reliability properties of the studied systems. The first studied system consists of a non-conformal CVD O3 TEOS liner, an ALD TiN barrier and a PVD Cu seed. The second studied system employs a conformal ALD liner, a thermal ALD WN barrier and an ELD NiB seed. Both studied systems show excellent reliability properties. Scalable highly conformal liners are more sensitive to local field enhancement at the high fields applied during highly accelerated tests which are far above normal operation conditions. Their performance at lower fields, however, still meets standard reliability specifications.

An alternative approach to backside via reveal (BVR) for a via-middle through-Silicon via (TSV) flow

An alternative scheme has been developed to combine three major backside via reveal (BVR) processes, including (a) wafer polishing, (b) Si recess etching, and (c) wet clean, into an integrated wet etch process to replace the high cost chemical-mechanical planarization (CMP) and dry etching steps. The process combines two steps on a single-wafer platform: (1) bulk Si etching chemistry with high etch rate (>10 μm/min.) to replace the CMP or polishing and (2) selective Si etching chemistry (Si: SiO2 ~ 1800:1) to replace the Si recess dry etching step. Using this process, Si thickness uniformity can be significantly improved (for 20 μm Si removal), resulting in a lower variation in step height of through-Si via (TSV) protrusion across a 300 mm wafer. The overall cost is significantly lower than CMP plus dry etching. After the integrated wet etching process, passivation layers of low-temperature silicon nitride and oxide were deposited on the backside, followed by CMP to planarize the wafer and expose the Cu nails. The film adhesion is very good without showing any film delamination or peeling. This new integration scheme is robust with a wide process margin and provides cost savings over the conventional BVR flow.

Unbiased roughness measurements: the key to better etch performance

Edge placement error (EPE) has become an increasingly critical metric to enable Moore’s Law scaling. Stochastic variations, as characterized for lines by line width roughness (LWR) and line edge roughness (LER), are dominant factors in EPE and known to increase with the introduction of EUV lithography. However, despite recommendations from ITRS, NIST, and SEMI standards, the industry has not agreed upon a methodology to quantify these properties. Thus, differing methodologies applied to the same image often result in different roughness measurements and conclusions. To standardize LWR and LER measurements, Fractilia has developed an unbiased measurement that uses a raw unfiltered line scan to subtract out image noise and distortions. By using Fractilia’s inverse linescan model (FILM) to guide development, we will highlight the key influences of roughness metrology on plasma-based resist smoothing processes. Test wafers were deposited to represent a 5 nm node EUV logic stack. The patterning stack consists of a core Si target layer with spin-on carbon (SOC) as the hardmask and spin-on glass (SOG) as the cap. Next, these wafers were exposed through an ASML NXE 3350B EUV scanner with an advanced chemically amplified resist (CAR). Afterwards, these wafers were etched through a variety of plasma-based resist smoothing techniques using a Lam Kiyo conductor etch system. Dense line and space patterns on the etched samples were imaged through advanced Hitachi CDSEMs and the LER and LWR were measured through both Fractilia and an industry standard roughness measurement software. By employing Fractilia to guide plasma-based etch development, we demonstrate that Fractilia produces accurate roughness measurements on resist in contrast to an industry standard measurement software. These results highlight the importance of subtracting out SEM image noise to obtain quicker developmental cycle times and lower target layer roughness.

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module

An advanced TSV metallization scheme, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling is presented. Because of the high conformality of the WN barrier and NiB seed, very thin layers can be deposited, reducing the manufacturing cost significantly, while still guaranteeing continuous barrier/seed layers all along the TSV sidewall to the bottom of the TSV. 3 × 50μm via-middle wafers, processed with this metallization scheme, are further processed through the thinning module, by using temporary bonded carriers, the backside passivation module and a copper RDL module by using a semi-additive process. The TSV resistance is measured between the 5μm thick RDL copper layer at the back side and the METPASS aluminum layer at the wafer front side. Low spread and high yield is obtained on the resistance data distribution of both single kelvin and daisy chain structures. The same metallization scheme is successfully scaled to a 2μm diameter and 40μm deep via-middle module. The conformal deposition of the barrier and the seed layer enables further scaling down to aspect ratio 20:1 through silicon vias with 5μm pitch, still ensuring the void-free bottom up copper fill by electroplating. The integrity of the liner/barrier system against Cu diffusion from TSV to silicon has been verified using the established controlled I-V method. Field acceleration factors, extracted in both copper-confined and copper-driven regime, indicate good TDDB reliability of this advanced 2 × 40μm TSV middle module.

Cu electromigration improvement by adhesion promotion treatment (APT)

A new process to promote adhesion between the SiC diffusion barrier and Cu was developed to achieve significant improvement in electromigration of the Cu interconnect without sacrificing RC delay, line-to-line leakage, breakdown voltage and time-dependent-dielectric-breakdown. An in-situ treatment of the wafer surface inserted between the sequential processes of Cu pretreatment and SiC deposition increased the Cu/SiC interfacial adhesion by more than 30%. Electrical and physical characterization data is presented that demonstrates the improvement in reliability metrics of the interconnect using the newly developed process, while limiting the RC change to < 1%.