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Dive into the research topics where Girish Dixit is active.

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Featured researches published by Girish Dixit.


Journal of The Electrochemical Society | 2003

Planarization of Copper Thin Films by Electropolishing in Phosphoric Acid for ULSI Applications

Deenesh Padhi; Joseph Yahalom; Srinivas Gandikota; Girish Dixit

Electropolishing of thin films poses additional challenges in comparison to hulk material polishing. The existence of a resistive anode/electrolyte boundary layer is crucial for achieving polishing. A finite amount of copper is required to he anodically dissolved to create the boundary layer of the appropriate thickness for effective electropolishing of a given hillock. This is a significant consideration in the application of electropolishing for planarization of thin films where the disparity in the topography is significant in proportion to the thickness of the film. Here electropolishing is shown to effectively remove the bulk of electrodeposited copper layers used in ultralarge scale integration (ULSI) metallization schemes without application of mechanical force and to planarize local topography. Efficient polishing can be achieved under galvanostatic conditions (i.e., constant current between the wafer and a counter electrode). Anodic transient studies indicated that the mechanism of formation of the boundary layer (in mass-transport controlled regime) is determined by the diffusive transport of an acceptor species to the anode/electrolyte Interface. Effects of changes in current density and rotational speed of wafer on the extent of planarization have heen determined. Under optimal galvanostatic and hydrodynamic conditions, the disparity in the topography over wide trenches adjacent to dense features decreased by 60%.


Electrochimica Acta | 2003

Electrodeposition of copper–tin alloy thin films for microelectronic applications

Deenesh Padhi; Srinivas Gandikota; Hoa B. Nguyen; Chris McGuirk; Sivakami Ramanathan; Joseph Yahalom; Girish Dixit

The continuing shrink in device size has generated great interest to create interconnects with low resistivity and superior resistance to electromigration (EM) and stress migration (SM) in comparison to the existing Al or Al-alloy interconnections. Copper has become the metal of choice to meet the needs of present and future generation devices. In order to improve the intrinsic resistance of copper to EM/SM induced failure, alloying elements can be added into copper metallurgy. In the present investigation, we discuss a method to co-deposit an alloy of copper and tin in sub-microscopic features with high aspect ratio using a sulfate bath. It is observed that a small amount tin begins to co-deposit at potentials smaller than the equilibrium reduction potential. Under activation control regime, the composition is not affected by current density. The results of this study conclude that substantial tin deposition occurs upon onset of mass-transport limitation. It is found that a finite amount of time is required before electrolysis is controlled by mass-transfer. The transition time and hence, the composition of the plated film is affected by the hydrodynamic conditions, current density, and electrolyte composition. These factors must be taken into account in order to control the composition profile of tin in vias and trenches.


Journal of Applied Physics | 2003

Effect of electron flow direction on model parameters of electromigration-induced failure of copper interconnects

Deenesh Padhi; Girish Dixit

This investigation studies the effects of the direction of electron flow on the activation energy and current exponent of electromigration failure of copper interconnects using conductors terminated by vias at both ends. The activation energy of a downstream case (0.91 eV) was found to be similar to that of an upstream case (0.86 eV), suggesting that failure was primarily caused by diffusion along the Cu/SiNx interface for both cases. Mean time to fail with the upstream flow condition exceeded that with the downstream condition by a factor of ∼2 at 300 °C and 1(106) A/cm2. The current exponent (with a link current density in the range of 1×106 to ∼5×106 A/cm2) of a 0.22 μm via/link structure was determined to be 1.44 and 1.87 with upstream and downstream electron flow, respectively. These differences have been correlated to the locations of void nucleation and their physical size for the two electron flow conditions. Furthermore, increasing the via/link size resulted in a slight increase in the current exponent, consistent with the model proposed by Lloyd [J. R. Lloyd, J. Appl. Phys. 69, 7601 (1991).]This investigation studies the effects of the direction of electron flow on the activation energy and current exponent of electromigration failure of copper interconnects using conductors terminated by vias at both ends. The activation energy of a downstream case (0.91 eV) was found to be similar to that of an upstream case (0.86 eV), suggesting that failure was primarily caused by diffusion along the Cu/SiNx interface for both cases. Mean time to fail with the upstream flow condition exceeded that with the downstream condition by a factor of ∼2 at 300 °C and 1(106) A/cm2. The current exponent (with a link current density in the range of 1×106 to ∼5×106 A/cm2) of a 0.22 μm via/link structure was determined to be 1.44 and 1.87 with upstream and downstream electron flow, respectively. These differences have been correlated to the locations of void nucleation and their physical size for the two electron flow conditions. Furthermore, increasing the via/link size resulted in a slight increase in the current e...


international interconnect technology conference | 2001

Thermal stress and reliability characterization of barriers for Cu interconnects

K. Musaka; B. Zheng; H. Wang; K. Wijkekoon; Liang-Yuh Chen; J. Lin; K. Watanabe; K. Ohira; T. Hosoda; K. Miyata; T. Hasegawa; Girish Dixit; R. Chueng; M. Yamada; S. Kadomura

MOCVD TiSiN was evaluated as a barrier for Cu interconnects application. The TiSiN film was formed by SiH/sub 4/ soaking of MOCVD TiN. The TiSiN film showed improved wetting and adhesion to Cu as well as less stress hysteresis in its integration with Cu. The low stress hysteresis yields higher resistance to Cu void generation during hot storage testing. Electrical tests on DLM Cu test structures demonstrated comparable line and via chain resistance and equivalent line-to-line leakage current in BTS testing compared to conventional PVD Ta(N).


Journal of Materials Research | 2004

A sample preparation method for four point bend adhesion studies

Zhenjiang Cui; Sure Ngo; Girish Dixit

A method to prepare samples for four point bend testing is reported in this paper. The traditional method of sample preparation involves time-consuming steps of sawing with a diamond saw followed by polishing with fine grit to remove the roughness of the sidewall. The new method uses cleaving along the (100) crystallographic direction, which renders smooth surfaces and eliminates the polishing steps. Load-displacement curves comparing polished versus cleaved samples show that the new technique provides improved results. Elimination of fracture-inducing defects is the primary benefit of this method, which also leads to data with tighter distributions.


Characterization and Metrology for ULSI Technology | 2005

Benchmarking Four Point Bend Adhesion Testing: The Effect of Test Parameters On Adhesion Energy

Zhenjiang Cui; Girish Dixit; Li-Qun Xia; Alex Demos; Bok Heon Kim; Hichem M’saad; Reinhold H. Dauskardt

The four‐point bend test method has been widely used to quantify the adhesion energy of interfaces in multilayer thin film stacks. However, the adhesion energy of an interface (Gc) may be effected by variances in the specimen preparation method and test procedure. In the present study, a less time consuming method of specimen preparation that involved cleaving (DPN‐free method) rather than dicing of specimen was found to offer a 90% test success rate with high accuracy and repeatability. The epoxy curing temperature and time were minor factors affecting Gc and their effect was within the test standard deviation of 0.3 J/m2. For a higher Gc interface, the epoxy thickness was found to result in a 20% increase in measured Gc as the bond layer was increased from 7 to 50 μm. The measured value of Gc also increased by 20% as the displacement rate was increased from 0.05 μm/s to 0.5 μm/s. The notch or scribe used to initiate the crack was found in one stack structure to have an effect on the interface that debonded. The delamination interface can be modulated through control of the notching step during sample preparation.


international interconnect technology conference | 2003

Enhancing the electromigration resistance of copper interconnects

Girish Dixit; Deenesh Padhi; Srinivas Gandikota; J. Yahalom; S. Parikh; N. Yoshida; K. Shankaranarayanan; J. Chen; N. Maity; J. Yu

Various factors such as grain boundary/surface diffusion as well as structural properties of materials are known to affect the final electro-migration (EM) behavior of copper interconnections. Results presented in this paper show that the barrier layer has a strong influence in controlling the width of EM failure distributions. EM tests of samples with alternate barrier, fill and capping layers show that atomic layer chemical vapor deposited (ALCVD) barrier and/or metallic cap layers are key to realize structures with superior EM lifetimes.


international interconnect technology conference | 2004

Film properties and integration performance of a nano-porous carbon doped oxide

Girish Dixit; Lester A. D'Cruz; Sang Ahn; Yi Zheng; J. Chang; Mehul Naik; Alexandros T. Demos; Hichem M'Saad

A porous carbon doped oxide has been developed using a conventional PECVD reactor. Sequential electron beam treatment using a flood beam provides a means for removal of the thermally labile organic species and results in a porous material with high thermal stability. Film properties and integration results presented show the viability of integrating this film into a conventional dual damascene interconnect flow.


international interconnect technology conference | 2011

Process integration of iALD TaN for advanced Cu interconnects

Hui-Jung Wu; Sanjay Gopinath; Kenneth Jow; Emery Kuo; Victor Lu; Kie-Jin Park; Roey Shaviv; Tom Mountsier; Girish Dixit

A high density/low resistivity TaN film grown using ion-induced atomic layer deposition (iALD) has been developed as the metal barrier for nano-scale Cu interconnects. Excellent conformalilty and Cu barrier performance enable the use of thin iALD TaN as the metal barrier. Integration of this film has demonstrated improvement in line and via resistance while maintaining robust electromigration (EM), via stress migration (VSM), and dielectric reliability performance.


international interconnect technology conference | 2004

300mm copper low-k integration and reliability for 90 and 65 nm nodes

Suketu A. Parikh; Mehul Naik; Raymond Hung; Huixiong Dai; Deenesh Padhi; Luke Zhang; Tony Pan; Kuo-Wei Liu; Girish Dixit; Michael D. Armacost

The paper addresses critical issues associated with 90 and 65 nm copper low k interconnects. A stable baseline with >98% yield on 1E7via and 5m long serpent was established. Electromigration (EM) and IV breakdown performance was improved by optimizing the post CMP Cu pre-treatment and the dielectric barrier obtaining EM T/sub 0.1/ lifetime of greater than 10 yrs at 1.5 MA/cm/sup 2/ and >6MV/cm IV breakdown field. Detailed characterization of the impact of the barrier process on stress migration (SM) is presented. Extendibility of the process flow to sub-90nm interconnects and advanced dielectric (k<2.7) is shown.

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