Praveen Nalla

Cobalt bottom-up contact and via prefill enabling advanced logic and DRAM technologies

This work introduces two new metallization schemes using the electroless deposition (ELD) technique; one based on contact fill and one based on via prefill. One of the key features of the electroless process is its selective deposition, which can be used for bottom-up fill of high aspect ratio features. The feasibility of this Co ELD process is demonstrated on contacts landing on W and vias landing on Cu. Our simulation of the Co via resistance shows that it can serve as alternative to Cu with lower via resistance below 15nm dimension. The results from a planar capacitor study show that there is no degraded reliability in an organo-silicate glass low-k film when Co is in direct contact with this dielectric. Therefore, selective Co ELD process for contact and via prefill has the potential to enable future scaling of advanced logic and DRAM technologies.

Advanced metallization scheme for 3×50µm via middle TSV and beyond

An advanced Via-Middle TSV metallization scheme is presented, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling process. Because of the high conformality of the WN barrier and NiB seed, these layers can be deposited very thinly, reducing the cost significantly, while still guaranteeing continuous barrier/seed layers all along the TSV sidewall till the bottom of the TSV. This metallization scheme has been successfully processed on 3 m diameter and 50 m deep Via-Middle TSVs, showing void-free copper fill in FIB cross-sections. Good adhesion between liner, barrier and seed was maintained during the processing, including the post plate anneal which is present to reduce the copper pumping. The polishing of the NiB seed and WN barrier has been optimized in order to limit the recess of these layers at the top of the TSV. Electrical results are shown, proving the maturity of this new TSV middle process scheme. Low leakage current in both accumulation and depletion mode is measured. The flat band voltage is low as well, indicating little ionic contamination in the liner oxide. The intrinsic integrity of the liner and the ability of the barrier to prevent Cu diffusion from TSV to silicon has been verified, using the established controlled I-V method. High field acceleration factors are extracted, ensuring good reliability of this advanced and scalable 3×50 TSV middle module.

Advanced integrated metallization enables 3D-IC TSV scaling

Innovative solutions have been developed to address the challenges of through-silicon via (TSV) metallization with small sizes and high aspect ratios. We demonstrate an advanced metallization scheme including conformal film depositions of metal barrier and seed with excellent sidewall coverage to achieve void-free Cu fill in small-size (10 to 1 μm) TSV with high aspect ratio (10:1 to 20:1). In addition, it reduces the field metal thickness to significantly lower the costs of metallization and subsequent CMP. TSVs fabricated using this new process integration scheme exhibited higher breakdown voltage and lower leakage current than those made with the conventional PVD barrier seed. No degradation in performance was observed after 400°C annealing and thermal cycling. The improved performance is attributed to the formation of pinhole-free metal barrier layer with excellent sidewall coverage.

Development of electroless Co via-prefill to enable advanced BEOL metallization and via resistance reduction

A novel metallization scheme was developed to enable advanced BEOL interconnect scaling. The proposed approach adopts electroless Co to selectively grow Co in vias, followed by conventional Cu metallization for the trench. We have demonstrated the feasibility of this approach through the process integration of electroless Co via pre-fill on a two metal layer interconnect test structure. A detailed discussion on the yield improvement, parametric data, and reliability will be presented in this paper.

An alternative approach to backside via reveal (BVR) for a via-middle through-Silicon via (TSV) flow

An alternative scheme has been developed to combine three major backside via reveal (BVR) processes, including (a) wafer polishing, (b) Si recess etching, and (c) wet clean, into an integrated wet etch process to replace the high cost chemical-mechanical planarization (CMP) and dry etching steps. The process combines two steps on a single-wafer platform: (1) bulk Si etching chemistry with high etch rate (>10 μm/min.) to replace the CMP or polishing and (2) selective Si etching chemistry (Si: SiO2 ~ 1800:1) to replace the Si recess dry etching step. Using this process, Si thickness uniformity can be significantly improved (for 20 μm Si removal), resulting in a lower variation in step height of through-Si via (TSV) protrusion across a 300 mm wafer. The overall cost is significantly lower than CMP plus dry etching. After the integrated wet etching process, passivation layers of low-temperature silicon nitride and oxide were deposited on the backside, followed by CMP to planarize the wafer and expose the Cu nails. The film adhesion is very good without showing any film delamination or peeling. This new integration scheme is robust with a wide process margin and provides cost savings over the conventional BVR flow.

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module

An advanced TSV metallization scheme, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling is presented. Because of the high conformality of the WN barrier and NiB seed, very thin layers can be deposited, reducing the manufacturing cost significantly, while still guaranteeing continuous barrier/seed layers all along the TSV sidewall to the bottom of the TSV. 3 × 50μm via-middle wafers, processed with this metallization scheme, are further processed through the thinning module, by using temporary bonded carriers, the backside passivation module and a copper RDL module by using a semi-additive process. The TSV resistance is measured between the 5μm thick RDL copper layer at the back side and the METPASS aluminum layer at the wafer front side. Low spread and high yield is obtained on the resistance data distribution of both single kelvin and daisy chain structures. The same metallization scheme is successfully scaled to a 2μm diameter and 40μm deep via-middle module. The conformal deposition of the barrier and the seed layer enables further scaling down to aspect ratio 20:1 through silicon vias with 5μm pitch, still ensuring the void-free bottom up copper fill by electroplating. The integrity of the liner/barrier system against Cu diffusion from TSV to silicon has been verified using the established controlled I-V method. Field acceleration factors, extracted in both copper-confined and copper-driven regime, indicate good TDDB reliability of this advanced 2 × 40μm TSV middle module.