Jenn-Hwa Huang

A manufacturable complementary GaAs process

A self-aligned complementary GaAs heterostructure FET process has been established for low power, high-speed digital circuits. The devices are fabricated on four-inch MBE epitaxial wafers consisting of AlGaAs/InGaAs epilayers grown on LEC GaAs substrates. The process uses twelve lithographic steps including two levels of interconnect metal. Typical transconductances of 250 mS/mm and 60 mS/mm are achieved on 1/spl times/10 /spl mu/m N-channel and P-channel devices, respectively. Twenty-three stage unloaded complementary ring oscillators consisting of 1/spl times/10 /spl mu/m N- and P-FETs show propagation delay of 190 ps and speed-power product of 7.5 fJ or 0.35 /spl mu/W/MHz.<<ETX>>

Manufacturable GaAs VFET for power switching applications

We have developed a manufacturable process to fabricate high performance GaAs vertical field effect transistors (VFETs). Our process uses ion implantation to form the gate as opposed to previous VFET processes, which used epitaxial regrowth or angled evaporation. In this process, trenches 1.2 /spl mu/m wide by 0.6 /spl mu/m deep with a period of 2.4 /spl mu/m are formed by reactive ion etch (RIE) then the gate region is formed at the bottom of the trench by Ar/C ion co-implantation. Current handling capability of these devices exceeds 200 A/cm/sup 2/ with a specific on-resistance of 0.25 m/spl Omega/-cm/sup 2/ and calculated delay times of 13.9 ps.

Metamorphic InAlAs/InGaAs enhancement mode HEMTs on GaAs substrates

In/sub 0.5/Al/sub 0.5/As/In/sub 0.5/Ga/sub 0.5/As HEMTs have been grown metamorphically on GaAs substrates oriented 6/spl deg/ off [100] toward [111]A using a graded InAlAs buffer. The devices are enhancement mode and show good dc and RF performance. The 0.6-/spl mu/m gate length devices have saturation currents of 262 mA/mm at a gate bias of 0.7 V and a peak transconductance of 647 mS/mm. The 0.6 /spl mu/m/spl times/3 mm devices tested on-wafer have output powers up to 30 mW/mm and 46% power-added-efficiency (PAE) at 1 V drain bias and 850 MHz. When biased and matched for best efficiency performance, this same device has up to 68% PAE at V/sub d/=1 V.

A true enhancement mode single supply power HFET for portable applications

A true enhancement mode heterojunction FET has been developed for low voltage, high efficiency power amplifier applications. A 12 mm wide/spl times/1.0 /spl mu/m gate length device-with no additional circuitry-and only a single voltage supply of 3.5 V exhibited a power output of +31.5 dBm with 75% power-added efficiency at a power gain of 11.6 dB at 850 MHz.

Device and process optimization for a low voltage enhancement mode power heterojunction FET for portable applications

This paper describes a true enhancement mode RF power device with state-of-the-art performance operated at 3.5 Volts at 900 MHz. The performance was realized with a technology derived from the digital CGaAs/sup TM/ technology. The necessary device and process optimizations to adapt the digital technology for RF applications are discussed and results presented.

0.9 V DSP blocks: a 15 ns 4 K SRAM and a 45 ns 16-bit multiply/accumulator

4-k SRAM and 16-b multiply/accumulate DSP blocks have been designed and fabricated in complementary heterostructure GaAs. Both circuits operate from 1.5 V to below 0.9 V. The SRAM uses 28,272 transistors in an area of 2.44 mm/sup 2/. Cell size is 278 /spl mu/m/sup 2/ at 1.0-/spl mu/m gate length. Measured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, the power dissipated is 0.36 mW. The CGaAs multiplier uses a 16-b modified Booth architecture with a 3-way 40-b accumulator. The multiplier uses 11,200 transistors in an area of 1.23 mm/sup 2/. Measured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V. At 0.9 V, current is less than 0.4 mA. >

Anisotype-gate self-aligned p-channel heterostructure field-effect transistors

A new self-aligned p-channel HFET structure was evaluated for application to complementary HFET (CHFET) circuits. The AlGaAs/InGaAs HFET structure uses an anisotype graded N+ InGaAs/GaAs semiconductor gate to enhance the barrier height of the FET, resulting in a significant reduction in gate leakage current at low voltages. The anisotype PFET also uses a non-alloyed graded InGaAs/GaAs ohmic contacts that are stable to temperature as high as 550 degrees C. With AlGaAs composition of x=0.3, and a thin AlAs spacer of 60AA, leakage current was reduced by a factor of about 1000 at gate voltage of 1 V, when compared to AlGaAs/InGaAs HIGFET of aluminum content x=0.75. The anisotype PFET maintains high device transconductance, typically 50 mS/mm for 1.3 x 10 mu m PFETs, high reverse breakdown voltages, 9-10 V, and low capacitance. Microwave S-parameter characterization resulted in F/sub t/ of 5 GHz for a 1*50 mu m PFET. >

P-HEMTs for low-voltage portable applications using filled gate fabrication process

A fundamental change in gate formation to a filled gate process was combined with changes in film deposition. The resulting p-HEMT manufacturing process gives much better performance for low-voltage RF amplification. At a drain voltage of 3.5 V, a 12-mm periphery device fabricated by this method is capable of 33 dBm output power with an associated power-added efficiency of greater than 75%.

Nonalloyed InGaAs/GaAs ohmic contacts for self‐aligned ion implanted GaAs heterostructure field effect transistors

Nonalloyed indium gallium arsenide (InGaAs) ohmic contacts were investigated and successfully applied to both n‐ and p‐type self‐aligned ion implanted heterostructure field effect transistors (HFETs). The key factor was to preserve the doping concentration and structure integrity of the InGaAs layer during implant activation. Specific contact resistances in the range of 5×10−6–2×10−5 Ω cm for n and p HFETs were realized with this structure and process.

A single supply device technology for wireless applications

Single supply power amplifiers have become the new paradigm in portable phone handsets due to the recent availability of HBT and pseudo enhancement mode PHEMT technology. We have developed a true enhancement mode heterostructure insulated-gate FET device (HIGFET) which is suitable for use in both digital and analog power amplifiers and in addition to this, shows promise for use in small signal receiver applications.