Carl L. Shurboff

A manufacturable complementary GaAs process

A self-aligned complementary GaAs heterostructure FET process has been established for low power, high-speed digital circuits. The devices are fabricated on four-inch MBE epitaxial wafers consisting of AlGaAs/InGaAs epilayers grown on LEC GaAs substrates. The process uses twelve lithographic steps including two levels of interconnect metal. Typical transconductances of 250 mS/mm and 60 mS/mm are achieved on 1/spl times/10 /spl mu/m N-channel and P-channel devices, respectively. Twenty-three stage unloaded complementary ring oscillators consisting of 1/spl times/10 /spl mu/m N- and P-FETs show propagation delay of 190 ps and speed-power product of 7.5 fJ or 0.35 /spl mu/W/MHz.<<ETX>>

0.9 V DSP blocks: a 15 ns 4 K SRAM and a 45 ns 16-bit multiply/accumulator

4-k SRAM and 16-b multiply/accumulate DSP blocks have been designed and fabricated in complementary heterostructure GaAs. Both circuits operate from 1.5 V to below 0.9 V. The SRAM uses 28,272 transistors in an area of 2.44 mm/sup 2/. Cell size is 278 /spl mu/m/sup 2/ at 1.0-/spl mu/m gate length. Measured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, the power dissipated is 0.36 mW. The CGaAs multiplier uses a 16-b modified Booth architecture with a 3-way 40-b accumulator. The multiplier uses 11,200 transistors in an area of 1.23 mm/sup 2/. Measured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V. At 0.9 V, current is less than 0.4 mA. >

Performance review of integrated CMOS VCO circuits for wireless communications

This paper reviews monolithically integrated CMOS voltage controlled oscillators (VCO) for wireless communications. The key challenges in VCO development include: design of a high Q tank on a substrate tailored for CMOS, multiband operation using a single VCO, enhanced manufacturability using digital frequency tuning, and optimization of the overall VCO topology for low power operation. Recent developments in each of these areas are examined and a comparison of various VCO topologies versus figure of merit (FOM) is presented.

Review of SiGe process technology and its impact on RFIC design

Reviews recently published SiGe BiCMOS technologies for RFIC design. Performance and integration trends in SiGe HBTs are discussed. Performance of passive devices, such as an inductor, plays a key role in RF design. We review approaches to realize high Q inductor on a Si substrate. Finally, interaction of HBT performance with design is illustrated through LNA design.