William J. Ooms

A manufacturable complementary GaAs process

A self-aligned complementary GaAs heterostructure FET process has been established for low power, high-speed digital circuits. The devices are fabricated on four-inch MBE epitaxial wafers consisting of AlGaAs/InGaAs epilayers grown on LEC GaAs substrates. The process uses twelve lithographic steps including two levels of interconnect metal. Typical transconductances of 250 mS/mm and 60 mS/mm are achieved on 1/spl times/10 /spl mu/m N-channel and P-channel devices, respectively. Twenty-three stage unloaded complementary ring oscillators consisting of 1/spl times/10 /spl mu/m N- and P-FETs show propagation delay of 190 ps and speed-power product of 7.5 fJ or 0.35 /spl mu/W/MHz.<<ETX>>

Anisotype-gate self-aligned p-channel heterostructure field-effect transistors

A new self-aligned p-channel HFET structure was evaluated for application to complementary HFET (CHFET) circuits. The AlGaAs/InGaAs HFET structure uses an anisotype graded N+ InGaAs/GaAs semiconductor gate to enhance the barrier height of the FET, resulting in a significant reduction in gate leakage current at low voltages. The anisotype PFET also uses a non-alloyed graded InGaAs/GaAs ohmic contacts that are stable to temperature as high as 550 degrees C. With AlGaAs composition of x=0.3, and a thin AlAs spacer of 60AA, leakage current was reduced by a factor of about 1000 at gate voltage of 1 V, when compared to AlGaAs/InGaAs HIGFET of aluminum content x=0.75. The anisotype PFET maintains high device transconductance, typically 50 mS/mm for 1.3 x 10 mu m PFETs, high reverse breakdown voltages, 9-10 V, and low capacitance. Microwave S-parameter characterization resulted in F/sub t/ of 5 GHz for a 1*50 mu m PFET. >

Nonalloyed InGaAs/GaAs ohmic contacts for self‐aligned ion implanted GaAs heterostructure field effect transistors

Nonalloyed indium gallium arsenide (InGaAs) ohmic contacts were investigated and successfully applied to both n‐ and p‐type self‐aligned ion implanted heterostructure field effect transistors (HFETs). The key factor was to preserve the doping concentration and structure integrity of the InGaAs layer during implant activation. Specific contact resistances in the range of 5×10−6–2×10−5 Ω cm for n and p HFETs were realized with this structure and process.

NiZnAl-based p-type ohmic contacts on AlGaAs/InGaAs heterostructures

p-type ohmic contacts based on Ni/Zn/Al/TiWN metallization were evaluated for application to self-aligned p-channel heterostructure FETs. Low-resistance, stable ohmic contacts were achieved on Al/sub x/Ga/sub 1-x/As/InGaAs heterostructures with aluminum composition (x) as high as 0.75. Following short-term annealing of 30 s in the temperature range of 500 degrees C to 600 degrees C, contact resistances less than 0.6 Omega -mm and specific resistivities under 5*10/sup -6/ Omega -cm/sup 2/ were achieved. Further anneal at 500 degrees C for 10 min resulted in a minimum contact resistance of 0.06 Omega -mm and a specific resistivity of 3.2*10/sup -8/ Omega -cm/sup 2/. Contact morphology was mirror-smooth and specular and the contacts were found to be stable at 500 degrees C for anneal times as long as 40 min, with contact resistance remaining below 1 Omega -mm. >