Jennifer Tseng
Applied Materials
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Featured researches published by Jennifer Tseng.
Applied Physics Letters | 1996
Michal Danek; Marvin Liao; Jennifer Tseng; Karl A. Littau; D. Saigal; H. Zhang; Roderick Craig Mosely; M. Eizenberg
In situ, nitrogen rf plasma treatment of organometallic chemical vapor deposited (OMCVD) TiN, synthesized by thermal decomposition of tetrakis(dimethylamido) titanium, yielded films with low resistivity and enhanced chemical stability. A sequential OMCVD‐plasma treatment process allowed deposition of films with bulk resistivity as low as 400 μΩ cm. The nitridation resulted in reduction of the carbon concentration in the films, and crystallization of TiN. The composition and electrical properties of the nitridized films were found to be stable upon air exposure. The films possess excellent step coverage (≳70% in 0.35 μm device structures with aspect ratio ∼3) and low defect density (∼0.06 cm−2 for defect size ≥0.2 μm).
electronic components and technology conference | 2012
Niranjan Kumar; Sesh Ramaswami; John O. Dukovic; Jennifer Tseng; Ran Ding; Nagarajan Rajagopalan; Brad Eaton; Rohit Mishra; Rao Yalamanchili; Zhihong Wang; Sherry Xia; Kedar Sapre; John Hua; Anthony Chan; Glen T. Mori; Bob Linke
An overview is given of developments in unit-process and process-integration technology enabling the realization of through-silicon vias (TSVs) for 3D chip stacking. TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1-3]. The fabrication sequences for forming TSVs in the middle of the line (via-middle approach) and for revealing them from the backside in the far back end of the line are described with detailed attention to major unit processes of etch, dielectric deposition, barrier and seed deposition, electrochemical deposition, and chemical-mechanical planarization. Unit-process advances are described in relation to the structural and functional requirements of the TSVs, and examples are given of co-optimization among the interdependent steps of the integrated sequence. Emphasis is given to copper vias of diameter 4 to 10μm with aspect ratio between 8 and 12. For both the viaformation and via-reveal sequence, it is shown how integration problems were overcome by a comprehensive approach.
international interconnect technology conference | 2009
Paul F. Ma; Qian Luo; Arvind Sundarrajan; Jiang Lu; Joseph F. Aubuchon; Jennifer Tseng; Niranjan Kumar; Motoya Okazaki; Yuchun Wang; You Wang; Yufei Chen; Mehul Naik; Ismail T. Emesh; Murali Narasimhan
Physical vapor deposited (PVD) Cu seed layers have been successfully implemented for Cu gap-fill in feature sizes for the 2x nm flash devices. By tuning the incident angle of the incoming flux of Cu ions as well as utilizing the resputtering parameter, the overhang, sidewall coverage and asymmetry can be well controlled to enable complete fill by subsequent electrochemical deposition (ECD). Chemical vapor deposition (CVD) Cobalt (Co) films were also investigated as an enhancement layer for Cu gap-fill. It was observed that the insertion of a 1.5nm-thick CVD Co layer, deposited between a PVD Ta barrier and a Cu seed layer could effectively enhance gap-fill in the small geometry trench/via structures. The CVD Co enhancement layer could also significantly improve the electromigration (EM) resistance of the Cu interconnects. The Chemical Mechanical Polish (CMP) process was also developed to provide an integrated solution.
MRS Proceedings | 2008
Hsien-Lung Yang; Fuhong Zhang; Kim Nelson; Jennifer Tseng; John C. Forster; Arvind Sunddarrajan; Ajay Bhatnagar; Niranjan Kumar; Prabu Gopalraja
In Copper back-end-of-line (BEOL), the “punchthru™ process” – removal of barrier material from via bottom during etch/re-sputter step, and gouging into the underlying Copper line - has been increasingly used in 65nm production for its superior reliability. However, with the adoption of porous low-k dielectric at 45nm node and beyond, the conventional punchthru process can cause physical damage to the porous dielectric, such as roughening of the trench bottom in dual damascene structures, micro-trenching in the bottom of single trenches, which may have reliability implications. This paper reported on the use of off-angular Tantalum neutral flux during the re-sputter process to improve the selectivity between the via and trench bottom in order to protect the trench bottom and via bevel, while still allowing sufficient gouging into the underlying Copper line. In addition, the plasma density and ion energy are adjusted to further optimize selectivity, and to eliminate any micro-trenching. Therefore, this paper demonstrated PVD high deposit/etch selectivity process based on transmission-electron microscopy (TEM) and studies of electrical test result. This approach has extended the PVD Tantalum barrier process to at least 32nm node.
Archive | 2000
Robin Cheung; Yezdi Dordi; Jennifer Tseng
Archive | 1996
Chyi Chern; Wei Chen; Marvin Liao; Jennifer Tseng; Mei Chang
Archive | 1998
Jennifer Tseng; Mei Chang; Ling Chen; David C. Smith; Karl A. Littau; Chyi Chern; Marvin Liao
Archive | 2013
Paul F. Ma; Jennifer Tseng; Mei Chang; Annamalai Lakshmanan; Jing Tang
Archive | 1997
Marvin Liao; Chyi Chern; Jennifer Tseng; Michael Danek; Roderick Craig Mosely; Karl A. Littau; Ivo Raajmakers
Archive | 1996
Jennifer Tseng; Mei Chang; Ramanujapuram A. Srinivas; Klaus-Dieter Rinnen; M. Eizenberg; Susan Weihar Telford