Mehul Naik

Nucleation and growth of CVD Al on different types of TiN

Abstract The deposition of Al by CVD on top of a Ti/TiN liner is a very promising approach for filling gaps with a high aspect ratio. In this work we have studied the nucleation and growth of CVD Al and its bulk properties as a function of the type of TiN used. For a given type of TiN we deposited films over a wide range of thickness (5–300 nm). The depositions were carried out in a cluster tool (Endura™) where in some cases we deliberately allowed for a vacuum break prior to the Al deposition. Auger electron spectroscopy was used to measure the amount of Al deposited, thus yielding the kinetics of the Al growth. X-ray diffraction was used to determine the preferred orientation of the Al, which is important for electromigration resistance. The microstructure was studied by scanning and transmission electron microscopy and atomic force microscopy. We found that air exposure affects the nucleation, the rate of growth at the early stages, and the resultant morphology. A correlation exists between the nucleation stages of the growth and the bulk properties.

Optimized integrated copper gap-fill approaches for 2x flash devices

Physical vapor deposited (PVD) Cu seed layers have been successfully implemented for Cu gap-fill in feature sizes for the 2x nm flash devices. By tuning the incident angle of the incoming flux of Cu ions as well as utilizing the resputtering parameter, the overhang, sidewall coverage and asymmetry can be well controlled to enable complete fill by subsequent electrochemical deposition (ECD). Chemical vapor deposition (CVD) Cobalt (Co) films were also investigated as an enhancement layer for Cu gap-fill. It was observed that the insertion of a 1.5nm-thick CVD Co layer, deposited between a PVD Ta barrier and a Cu seed layer could effectively enhance gap-fill in the small geometry trench/via structures. The CVD Co enhancement layer could also significantly improve the electromigration (EM) resistance of the Cu interconnects. The Chemical Mechanical Polish (CMP) process was also developed to provide an integrated solution.

Texture and surface morphology improvement of Al by two-stage chemical vapor deposition and its integration in an Al plug-interconnect scheme for sub 0.25 μm metallization

A two-stage deposition with successive seed and bulk deposition steps was developed to improve the morphology and texture of chemical vapor deposited (CVD) aluminum on titanium. Dimethylaluminumhydride (DMAH) was used as the precursor. Typically, CVD Al deposited using a single deposition stage showed highly granular structure with surface “defects” resulting in films that become rough with increase in thickness creating integration problems with photolithography and etch. Here, a two-stage deposition process for CVD Al is described that significantly improves the morphology and texture of Al on titanium. In this process, the wafer surface is preconditioned with a short burst of DMAH before stabilizing gas flows or pressure. Such a treatment in the very first step results in a seed layer upon which proceeds the bulk film deposition in a subsequent step after stabilizing pressure, gas flows and equilibrating temperature. The two-stage deposition resulted in reflectivity improvement of CVD Al on Ti from ⩽ 1...

CVD Al/PVD Al integration for advanced via and interconnect technology

A metallization process that can fill the ever-shrinking vias and form the interconnect at the same time is highly desirable. An integrated Al plug and interconnect process offers advantages of improved electrical performance, and reduced cost of ownership through process simplification for 0.25 μm and beyond. In this report, an enabling technology that integrates Al deposited by chemical vapor deposition (CVD) with an overlayer of sputtered AlCu is discussed. The ability to deposit in-situ sequential layers without a vacuum break was a key factor in developing a technology for consistent void-free fill of sub-0.25 μm structures. This approach has resulted in a low resistivity (∼ 3 μΩ cm), low temperature ( < 380°C) via fill process with copper doping of CVD Al. Sub-0.2 μm via/contact fill with aspect ratio greater than 4 was achieved. This technology was integrated in a two-level 0.35 μm design rule with conventional BEOL processing. A better than 2 x improvement in via resistance was achieved compared to W technology. No problems were encountered with oxide CMP, photolithography or metal etch. Data on via fill capability and electrical performance of the integrated CVD Al/PVD AlCu process is presented. Studies on copper doping of CVD Al are discussed. Investigation of morphology and texture dependence on wetting layer for CVD Al is reported.

Novel Hardmask for Sub-20nm Copper/Low K Backend Dual Damascene Integration

As device nodes move below 20nm and increasing concerns for low k damage during plasma etch, alternative metal hardmask (HM) schemes have gained tractions for back-end-of-line (BEOL) integration. Conventional TiN hardmask has been in high volume manufacturing since the 90nm technology node, however, TiN faces many challenges, such as defectivity, line bending, and manufacturing robustness, which can only be overcome at the expense of shrinking the overall process window. A novel boron nitride (BN) based HM material was developed using a conventional CVD approach to address these issues.

Self-Aligned Double Patterning Process for 32/32nm Contact/Space and beyond using 193 Immersion Lithography

State of the art production single print lithography for contact is limited to ~43-44nm half-pitch given the parameters in the classic photolithography resolution formula for contacts in 193 immersion tool (k1 ≥ 0.3, NA = 1.35, and λ = 193nm). Single print lithography limitations can be overcome by (1) Process / Integration based techniques such as double-printing (DP), and spacer based self-aligned double patterning (SADP), (2) Non-standard printing techniques such as electron-beam (eBeam), extreme ultraviolet lithography (EUVL), nano-imprint Lithography (NIL). EUV tools are under development, while nanoimprint is a developmental tool only. Spacer based SADP for equal line/space is well documented as successful patterning technique for 3xnm and beyond. In this paper, we present an adaptation of selfaligned double patterning process to 2-D regular 32/32nm contact/space array. Using SADP process, we successfully achieved an equal contact/space of 32/32nm using 193 immersion lithography that is only capable of 43-44nm resolvable half-pitch contact printing. The key and unique innovation of this work is the use of a 2-D (x and y axis) pillar structure to achieve equal contact/space. Final result is a dense contact array of 32nm half-pitch in 2-D structure (x and y axis). This is achieved on simplified stack of Substrate / APF / Nitride. Further transfer of this new contact pattern from nitride to the substrate (e.g., Oxide, APF, Poly, Si...) is possible. The technique is potentially extendible to 22/22nm contact/space and beyond.

Film properties and integration performance of a nano-porous carbon doped oxide

A porous carbon doped oxide has been developed using a conventional PECVD reactor. Sequential electron beam treatment using a flood beam provides a means for removal of the thermally labile organic species and results in a porous material with high thermal stability. Film properties and integration results presented show the viability of integrating this film into a conventional dual damascene interconnect flow.

Restoration and pore sealing of low-k films by UV-assisted processes

Porous low-k dielectrics are susceptible to damages by steps such as etch, ash, and CMP in the BEOL process flow. Such damages degrade the structural and electrical properties of low-k materials. To uphold the value of integrating low-k dielectrics, restoration processes are needed to repair such damages. In this work, UV-assisted silylation is used to repair damages and restore properties of porous low-k dielectrics. The repair process is able to restore carbon content, as indicated by the increase in water contact angle (WCA), and restore the electrical properties, as shown by the decrease in dielectric constant (k) and increase in break-down electrical field based on blanket-film data. On structured wafers, the post-etch repair process effects a 4-6% reduction in RC when compared to without repair. The same UV-assisted platform may be used to effect pore sealing to prevent metals used in BEOL metallization from penetrating into porous low-k materials. On structured wafers, the pore-sealing process is able to reduce Mn penetration into porous low-k when ALD MnN is used as the copper barrier.

Process development and integration of electroless cobalt cap with low k carbon doped oxide

Electroless CoWP was integrated with k/spl sim/3.0 carbon doped oxide using SiCN as the post CMP dielectric barrier. Process parameters that impacted leakage performance and line resistance increase were identified and resolved. Leakage performance equivalent to uncapped samples was obtained with minimal increase (0-2%) in line resistance for 90 nm node critical dimension. Via chain yields of >95% were obtained for 1 million via count chain with via resistance similar to uncapped samples. A >20x improvement in electromigration median time (T/sub 50/) was obtained at twice the current density of uncapped samples. Feasibility of direct low k deposition on CoWP is explored.

300mm copper low-k integration and reliability for 90 and 65 nm nodes

The paper addresses critical issues associated with 90 and 65 nm copper low k interconnects. A stable baseline with >98% yield on 1E7via and 5m long serpent was established. Electromigration (EM) and IV breakdown performance was improved by optimizing the post CMP Cu pre-treatment and the dielectric barrier obtaining EM T/sub 0.1/ lifetime of greater than 10 yrs at 1.5 MA/cm/sup 2/ and >6MV/cm IV breakdown field. Detailed characterization of the impact of the barrier process on stress migration (SM) is presented. Extendibility of the process flow to sub-90nm interconnects and advanced dielectric (k<2.7) is shown.