Paul F. Ma

CVD Co and its application to Cu damascene interconnections

Fundamental material interactions as pertinent to nano-scale copper interconnects were studied for CVD Co with a variety of micro-analytical techniques. Native Co oxide grew rapidly within a few hours (XPS). Incorporation of oxygen and carbon in the CVD Co films (by AES and SIMS) depended on underlying materials, such as Ta, TaN, or Ru. Copper film texture (by XRD) and agglomeration resistance (by AFM) showed correlations with amounts of in-film oxygen/carbon. Cobalt diffused through copper at normal processing temperatures (by SIMS). CVD Co demonstrated diffusion barrier performance to Cu (by Triangular Voltage Sweep, TVS), but not to O2. CVD Co was applied to 32 nm/22 nm damascene Cu interconnect fabrication in a scheme defined by the material studies. Lower post-CMP defect density and longer electromigration lifetimes were obtained.

Optimized integrated copper gap-fill approaches for 2x flash devices

Physical vapor deposited (PVD) Cu seed layers have been successfully implemented for Cu gap-fill in feature sizes for the 2x nm flash devices. By tuning the incident angle of the incoming flux of Cu ions as well as utilizing the resputtering parameter, the overhang, sidewall coverage and asymmetry can be well controlled to enable complete fill by subsequent electrochemical deposition (ECD). Chemical vapor deposition (CVD) Cobalt (Co) films were also investigated as an enhancement layer for Cu gap-fill. It was observed that the insertion of a 1.5nm-thick CVD Co layer, deposited between a PVD Ta barrier and a Cu seed layer could effectively enhance gap-fill in the small geometry trench/via structures. The CVD Co enhancement layer could also significantly improve the electromigration (EM) resistance of the Cu interconnects. The Chemical Mechanical Polish (CMP) process was also developed to provide an integrated solution.

CVD Co capping layers for Cu/low-k interconnects: Cu EM enhancement vs. Co thickness

Co films with various thicknesses were selectively deposited as Cu capping layers by chemical vapor deposition technique. Selectivity of the Co deposition between Cu and dielectric surfaces was improved by both raising the deposition pressure and adopting a pre-clean process prior to the Co deposition. Degree of electromigration resistance enhancement was observed to be dependent on the deposited Co thickness. Compared to the no-Co control, significant EM lifetime enhancement was observed when the Co cap is thicker than 6nm.

Metallization of sub-30 nm interconnects: Comparison of different liner/seed combinations

Narrow trenches with Critical Dimensions down to 17 nm were patterned in oxide using a sacrificial FIN approach and used to evaluate the scalability of TaN/Ta, RuTa, TaN + Co and MnOx metallization schemes. So far, the RuTa metallization scheme has proved to be the most promising candidate to achieve a successful metallization of 25 nm interconnects, providing high electrical yields and a good compatibility with the slurries used during CMP.

A conformal low resistivity fluorine free tungsten for FinFET metal gate and 3D memory applications

Tungsten has been the material of choice for contact and gate metallization, and continues to be used in FINFET architectures. In this work, we developed a low resistivity conformal Fluorine free tungsten film that can nucleate the WF6 based ALD/CVD W growth while blocking the fluorine diffusion from the bulk W fill material. It provides significant benefit in integration performance enhancement compare to common processes used for tungsten metallization.