Jenny Yi-Chun Liu

60 GHz CMOS Amplifiers Using Transformer-Coupling and Artificial Dielectric Differential Transmission Lines for Compact Design

57-65 GHz differential and transformer-coupled power and variable-gain amplifiers using a commercial 90 nm digital CMOS process are presented. On-chip transformers combine bias, stability and input/interstage matching networks to enable compact designs. Balanced transmission lines with artificial dielectric strips provide substrate shielding and increase the effective dielectric constant up to 54 for further size reduction. Consequently, the designed three-stage power amplifier occupies only an area of only 0.15 mm2. Under a 1.2 V supply, it consumes 70 mA and obtains small-signal gains exceeding 15 dB, saturated output power over 12 dBm and associated peak power-added efficiency (PAE) over 14% across the band. The variable-gain amplifier, based on the same principle, achieved a peak gain of 25 dB with 8 dB of gain variation.

Millimeter-Wave Self-Healing Power Amplifier With Adaptive Amplitude and Phase Linearization in 65-nm CMOS

A self-healing two-stage millimeter-wave broadband power amplifier (PA) with on-chip amplitude/phase compensation is realized in 65-nm CMOS. The amplitude and phase compensations are accomplished by using feedback bias/capacitive schemes to extend the linear operation region and optimize the PA efficiency. Tunable control knobs are inserted in the linearization block to enhance the PA performance yield against process/temperature variations and device ageing effects. This prototype shows a 5.5-dB improvement of the output 1-dB compression point (P1dB) and a less than 2% chip-to-chip gain variation. At a 1-V supply, the differential PA achieves a saturation output power (Psat) of 14.85 dBm with a peak power-added-efficiency (PAE) of 16.2%. With the amplitude compensation, P1dB is increased to 13.7 dBm. With the phase compensation, the output phase variation is decreased to less than 0.5°. To the best of our knowledge, this prototype provides the highest Psat and P1dB with simultaneously high PAE from a single PA reported to date. The PA delivers a linear gain of 9.7 dB and has a 7-GHz 3-dB bandwidth from 55.5 to 62.5 GHz with a compact total area of 0.042 mm2.

CMOS digital controlled oscillator with embedded DiCAD resonator for 58–64GHz linear frequency tuning and low phase noise

A digital controlled artificial dielectric (DiCAD) differential transmission line is embedded in 90nm CMOS to digitally tune a 58–64GHz DCO. DiCAD varies εr,eff from 18.8 to 32.5. A shunt open stub DiCAD provides discrete capacitive tuning with 13.1° S11 phase variation. The core oscillator is an inductively loaded differential, cross-coupled NMOS pair. Large nonlinear varactors are avoided, and the phase noise is better than −90dBc/Hz at 1MHz offset. Linear tuning bandwidth of 9.3% with a 61GHz center frequency occupying 0.01mm2 is achieved. Power consumption is 8.52mW with 1.2V.

A Wideband Inductorless Single-to-Differential LNA in

This study presents an inverter-based inductorless single-to-differential (S2D) wideband low-noise amplifier (LNA). The proposed LNA has three inverter-based gain stages with a global shunt feedback resistor for wideband input impedance matching. Moreover, a shunt capacitor with a current bias transistor in the third gain stage enhances the gain/phase imbalances and the linearity of the pseudo-differential outputs. When implemented in a TSMC 0.18- μm CMOS process, this wideband LNA covering DC-1.4 GHz achieves a S21 of 16.4 dB, a minimal input third-order intercept point (IIP3) of -13.3 dBm, and a minimal noise figure (with output buffers) of 3 dB. The output gain and phase imbalances are less than 1 dB and 2.5°, respectively, within 1 GHz. The chip consumes 12.8 mW from a 1.8 V supply.

0.18 \mu{\rm m}

A self-healing two-stage 60 GHz power amplifier (PA) with amplitude/phase compensation is realized in 65 nm CMOS. An adaptive feedback bias scheme with three control knobs is proposed to extend the linear operating region and enhance chip-to-chip performance yield; allowing a 5.5 dB improvement of the output 1-dB compression point (P1dB) and a less than 2% chip-to-chip gain variation. At a 1 V supply, the fully differential PA achieves a saturation output power (Psat) of 14.85 dBm with a peak power-added-efficiency (PAE) of 16.2%. With the on-chip amplitude compensation, the P1dB is extended to 13.7 dBm. With the on-chip phase compensation, the output phase variation is minimized to less than 0.5 degree. To the best of our knowledge, this PA provides the highest Psat and P1dB with simultaneous high PAE for a single PA reported to date. The PA delivers a linear gain of 9.7 dB and has a 7 GHz bandwidth from 55.5 to 62.5 GHz with a very compact area of 0.042 mm2.

CMOS Technology for Digital TV Receivers

The available ISM band from 57-65GHz has become attractive for high-speed wireless applications including mass data transfer, streaming high-definition video and even biomedical applications. While silicon based data transceivers at mm-wave frequencies have become increasingly mature in recent years [1,2,3], the primary focus of the circuit community remains on the design of mm-wave front-ends to achieve higher data rates through higher-order modulation and beamforming techniques. However, the sustainability of such mm-wave systems when integrated in a SoC has not been addressed in the context of die performance yield and device aging. This problem is especially challenging for the implementation of mm-wave SoCs in deep sub-micron technology due to its process & operating temperature variations and limited ft / fmax with respect to the operation frequency.

A V-band self-healing power amplifier with adaptive feedback bias control in 65 nm CMOS

A D-band CMOS power amplifier in 65-nm CMOS with wider than 30 GHz small signal gain bandwidth is developed by using proposed impedance transform network to split original matching network into 8-ways to integrate 8 transistors. Without using additional combining networks, the 4-stage power amplifier achieves 13.2 dBm saturation output power with 1.2 V supply at 140 GHz in a compact size of 0.38 mm2. The peak power-added efficiency is 14.6% with 115.2 mW dc power.

A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chip

A fully integrated three-stage 60 GHz power amplifier with amplitude/phase compensation is realized in 65 nm CMOS. An adaptive feedback bias scheme with three control knobs is proposed to extend the linear operating region. At a supply voltage of 1 V, the fully differential amplifier achieves a linear gain of 15 dB and occupies a compact area of 0.056 mm2. It achieves a minimal Psat-P1dB separation of 0.6 dB by extending the P1dB by 8.5 dB. To our best knowledge, this is the smallest Psat-P1dB separation reported to date. With on-chip phase compensation, the output phase variation is reduced by 57%.

A 1.2V broadband D-band power amplifier with 13.2-dBm output power in standard RF 65-nm CMOS

A digitally controlled artificial dielectric (DiCAD) differential transmission line is designed to perform agile linear phase shift over 100° with thermometer-coded 16step control. It also operates with a 16 gain-step VGA to enable re-configurable and direct-frequency modulation at 60GHz with 2562 states (1.1° angular and 0.0007 magnitude resolutions) and −31dB static EVM for multiple PSK/QAM modulations. The modulator uses 0.33mm2 core area in 90nm CMOS and consumes 10mA at 1V.

A 60 GHz Tunable Output Profile Power Amplifier in 65 nm CMOS

A direct conversion receiver which consists of low noise amplifier (LNA), mixer and programmable gain amplifier (PGA) for V-band (60GHz) applications is designed and realized in 65nm CMOS. A novel two-dimensional passive gm-enhancement technique is devised to boost the conversion gain and lower the Noise Figure (NF) with insignificant power overhead. An overall minimum SSB NF of 3.9dB and a maximum power conversion gain of 60dB have been validated from such fabricated receiver that occupies core silicon area of 0.2mm2 and draws 34mA from 1V supply.