Chih-Wen Lu

High-speed driving scheme and compact high-speed low-power rail-to-rail class-B buffer amplifier for LCD applications

A high-speed driving scheme and a compact high-speed low-power rail-to-rail class-B buffer amplifier, which are suitable for small- and large-size liquid crystal display applications, are proposed. The driving scheme incorporates two output driving stages in which the output of the first output driving stage is connected to the inverting input and that of the second driving stage is connected to the capacitive load. A compensation resistor is connected between the two output stages for stability. The second output stage is used to improve the slew rate and the settling time. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators to sense the transients of the input to turn on the output stages, which are statically off in the stable state. This increases the speed of the circuit without increasing static power consumption too much. A rail-to-rail folded-cascode differential amplifier is used to amplify the input signal difference and supply the bias voltages for the second stage. An experimental prototype output buffer implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the circuit draws only 7-/spl mu/A static current and exhibits the settling times of 2.7 /spl mu/s for rising and 2.9 /spl mu/s for falling edges for a voltage swing of 3.3 V under a 600-pF capacitance load with a power supply of 3.3 V. The active area of this buffer is only 46.5/spl times/57/spl mu/m/sup 2/.

A high-speed low-power rail-to-rail column driver for AMLCD application

A high-speed rail-to-rail low-power column driver for active matrix liquid crystal display application is proposed. An inversion controller is attached to a typical column driver for rail-to-rail operation. Two high-speed complementary differential buffer amplifiers are proposed to drive a pair of column lines and to realize a rail-to-rail and high-speed drive. The output buffer amplifier achieves a large driving capability by employing a simple comparator to sense the transients of the input to turn on an auxiliary driving transistor, which is statically off in the stable state. This increases the speed without increasing static power consumption. The experimental prototype 6-bit column driver implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the driver exhibits the maximum settling times of 1.2 /spl mu/s and 1.4 /spl mu/s for rising and falling edges with a dot inversion under a 680-pF capacitance load. The static current consumptions are 4.7 and 4.2 /spl mu/A for pMOS input buffers and nMOS input buffers, respectively. The values of the differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 1/2 LSB.

A 10-Bit LCD Column Driver With Piecewise Linear Digital-to-Analog Converters

A 10-bit LCD column driver, consisting of piecewise linear digital to analog converters (DACs), is proposed. Piecewise linear compensation is utilized to reduce the die area and to increase the effective color depth. The data conversion is carried out by a resistor string type DAC (R-DAC) and a charge sharing DAC, which are used for the most significant bit and least significant bit data conversions, respectively. Gamma correction voltages are applied to the R-DAC to lit the inverse of the liquid crystal trans-mittance-voltage characteristic. The gamma correction can also be digitally fine-tuned in the timing controller or column drivers. A prototype 10-bit LCD column driver implemented in a 0.35-mum CMOS technology demonstrates that the settling time is within 3 mus and the average die size per channel is 0.063 mm2, smaller than those of column drivers based exclusively on R-DACs.

A low-power high-speed class-AB buffer amplifier for flat-panel-display application

A low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer circuit, which is suitable for flat-panel display application, is proposed. The circuit employs an elegant comparator to sense the transients of the input to turn on charging/discharging transistors, thus draws little current during static, but has an improved driving capability during transients. It is demonstrated in a 0.6 /spl mu/m CMOS technology.

A 10-bit Resistor-Floating-Resistor-String DAC (RFR-DAC) for High Color-Depth LCD Driver ICs

This work proposes a novel resistor-floating-resistor-string digital-to-analog converter (RFR-DAC) architecture with a 10-bit resolution for liquid crystal display (LCD) driver applications. The proposed architecture improves the linearity of DAC, unifies its channel performance, and achieves a 10-bit resolution with a compact die size smaller than those of the state-of-the-art 10-bit DACs. The proposed RFR-DAC combines a 6-bit RDAC and a 4-bit FR-DAC (floating-resistor-string DAC) to offer unique two-voltage-selection and one-voltage-selection schemes without the need of unity-gain buffers to isolate parallel-connected resistor strings. A stacked floating class-AB control is also devised to bias the last output buffer stage. The 10-bit RFR-DAC prototypes are implemented using 0.35-μm/0.5-μm CMOS technology with the worst DNL/INL = 0.11/0.92 LSB via a two-voltage-selection scheme; and 1.37/1.45 LSB via a one-voltage-selection scheme.

A Rail-To-Rail Class-AB Amplifier With an Offset Cancellation for LCD Drivers

A rail-to-rail amplifier with an offset cancellation, which is suitable for high color depth and high-resolution liquid crystal display (LCD) drivers, is proposed. The amplifier incorporates dual complementary differential pairs, which are classified as main and auxiliary transconductance amplifiers, to obtain a full input voltage swing and an offset canceling capability. Both offset voltage and injection-induced error, due to the device mismatch and charge injection, respectively, are greatly reduced. The offset cancellation and charge conservation, which is used to reduce the dynamic power consumption, are operated during the same time slot so that the driving period does not need to increase. An experimental prototype amplifier is implemented with 0.35-mum CMOS technology. The circuit draws 7.5 muA static current and exhibits the settling time of 3 mus, for a voltage swing of 5 V under a 3.4 kOmega resistance, and a 140 pF capacitance load with a power supply of 5 V. The offset voltage of the amplifier with offset cancellation is 0.48 mV.

A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs

This work proposes a 10-b two-stage DAC with an area-efficient multiple-output voltage selector and a linearity-enhanced DAC-embedded op-amp for LCD column driver ICs. The proposed voltage selector is divided into two stages, MSB and LSB decoders; this design requires fewer switches compared with tree-type voltage selectors, enabling a smaller die area. The proposed 6-b two-voltage selector occupies only 61% of the area needed for a 6-b tree-type two-voltage selector. This study also develops a generalized architecture for an area-efficient voltage selector for multiple outputs. To improve the linearity of the DAC-embedded op-amp, the differential pairs operate at the edge of the saturation region. The 10-b DAC prototypes were produced with 0.35- μm/0.5- μm CMOS technology with the worst DNL/INL being 0.44/0.58 LSB.

A fast and sensitive built-in current sensor for IDDQ testing

In this work, a fast and highly sensitive Built-in Current (BIC) sensor is proposed for testing static CMOS ICs. The sensor employs a current mirror and an I-V converter to achieve the high sensing speed and high resolution. The circuit is simple and occupies a small area, making it ideal to be integrated into the IC chip for the IDDQ application.

A Wideband Inductorless Single-to-Differential LNA in

This study presents an inverter-based inductorless single-to-differential (S2D) wideband low-noise amplifier (LNA). The proposed LNA has three inverter-based gain stages with a global shunt feedback resistor for wideband input impedance matching. Moreover, a shunt capacitor with a current bias transistor in the third gain stage enhances the gain/phase imbalances and the linearity of the pseudo-differential outputs. When implemented in a TSMC 0.18- μm CMOS process, this wideband LNA covering DC-1.4 GHz achieves a S21 of 16.4 dB, a minimal input third-order intercept point (IIP3) of -13.3 dBm, and a minimal noise figure (with output buffers) of 3 dB. The output gain and phase imbalances are less than 1 dB and 2.5°, respectively, within 1 GHz. The chip consumes 12.8 mW from a 1.8 V supply.

0.18 \mu{\rm m}

Achieving a higher color depth for LCD drivers requires a higher DAC resolution and a larger circuit die area. Due to the stringent requirement on uniformity, a resistor-string DAC (RDAC) is predominantly used for LCD column drivers. However, the area of the RDAC and related routing lines are prohibitively large for a high-resolution data converter, making it impractical for column-driver ICs in high color depth displays [1].