Chewn-Pu Jou

High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration

Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLPs high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.

A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing

A low-phase-noise phase-locked loop (PLL) is widely used in clock generation, frequency synthesis, and data conversion. In a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power. In a low-phase-noise sub-harmonically injection-locked PLL (SIPLL) is presented. The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations. In addition, the divider of a SIPLL [3-5] cannot be powered down to save the power as in [1, 2]. In this paper, a divider-less SIPLL with self-adjusted injection timing is presented.

60GHz high-gain low-noise amplifiers with a common-gate inductive feedback in 65nm CMOS

In this paper, a novel design technique of common-gate inductive feedback is presented for millimeter-wave low-noise amplifiers (LNAs). For this technique, by adopting a gate inductor at the common-gate transistor of the cascode stage, the gain of the LNA can be enhanced even under a wideband operation. Using a 65nm CMOS process, transmission-line-based and spiral-inductor-based LNAs are fabricated for demonstration. With a dc power consumption of 33.6 mW from a 1.2-V supply voltage, the transmission-line-based LNA exhibits a gain of 20.6 dB and a noise figure of 5.4 dB at 60 GHz while the 3dB bandwidth is 14.1 GHz. As for the spiral-inductor-based LNA, consuming a dc power of 28.8 mW from a 1.2-V supply voltage, the circuit shows a gain of 18.0 dB and a noise figure of 4.5 dB at 60 GHz while the 3dB bandwidth is 12.2 GHz.

A Wideband Low Noise Amplifier With 4 kV HBM ESD Protection in 65 nm RF CMOS

This study presents a wideband low noise amplifier (LNA) including electrostatic discharge (ESD) protection circuits using 65 nm CMOS with a gate oxide thickness of only ~ 2 nm. By co-designing the ESD blocks with the core circuit, the LNA shows almost no performance degradation compared to the reference design without ESD. Under a power consumption of only 6.8 mW, the silicon results show that the LNA can achieve a peak power gain of 13.8 dB. Within the 3 dB bandwidth from 2.6 GHz to 6.6 GHz, the noise figure (NF) is in a range of 4.0 dB to 6.5 dB and the input reflection coefficient S 11 is below -13.0 dB. Using the miniaturized Shallow-Trench-Isolation (STI) diode of ~ 40 fF capacitance and a robust gate-driven power clamp configuration, the proposed LNA demonstrates an excellent 4 kV human body mode (HBM) ESD performance, which has the highest voltage/capacitance ratio ( ~ 100 V/fF) among the published results for RF LNA applications.

A Multi-ESD-Path Low-Noise Amplifier With a 4.3-A TLP Current Level in 65-nm CMOS

This paper studies the electrostatic discharge (ESD)-protected RF low-noise amplifiers (LNAs) in 65-nm CMOS technology. Three different ESD designs, including double-diode, modified silicon-controlled rectifier (SCR), and modified-SCR with double-diode configurations, are employed to realize ESD-protected LNAs at 5.8 GHz. By using the modified-SCR in conjunction with double-diode, a 5.8-GHz LNA with multiple ESD current paths demonstrates a 4.3-A transmission line pulse (TLP) failure level, corresponding to a ~ 6.5-kV Human-Body-Mode (HBM) ESD protection level. Under a supply voltage of 1.2 V and a drain current of 6.5 mA, the proposed ESD-protected LNA demonstrates a noise figure of 2.57 dB with an associated power gain of 16.7 dB. The input third-order intercept point (IIP3) is - 11 dBm, the input and output return losses are greater than 15.9 and 20 dB, respectively.

A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX

A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting a 802.15.3c heterodyne TRX is reported. The PLL can generate 6 equally spaced tones from 43.2GHz to 51.84GHz, which is suitable for a heterodyne architecture with LO=(4/5)RF. Phase noise is measured directly at the LO frequency and is better than −97.5dBc/Hz@1MHz across the entire band. The total power consumption is 72mW from a 1V supply. The reported frequency synthesizer is smaller, exhibits less phase noise, and consumes less power than prior art. In addition, the LO tone corresponds to the fundamental of the VCO as opposed to a higher harmonic. Central to the PLL performance is the design of a low-noise, mm-wave VCO with a 22.9% tuning range. It is noted that resonator nonlinearities may result in significant up-conversion of flicker noise in wideband, mm-wave VCOs. To overcome this, Digitally-Controlled-Artificial-Dielectric (DiCAD) is used to linearize the resonator.

Design of 60-GHz Low-Noise Amplifiers With Low NF and Robust ESD Protection in 65-nm CMOS

This paper presents two 60-GHz low-noise amplifiers (LNAs) with different electrostatic (ESD) protection schemes, including the diode-based and LC-based configurations. By codesigning ESD network and input matching, both LNAs are optimized for minimum noise figure (NF) while maintaining a similar gain. Compared with the conventional double-diode approach, the proposed LC-based design uses a high current capability spiral inductor and a high breakdown voltage metal-oxide-metal capacitor as effective bidirectional ESD protection, showing much improved ESD protection level and NF under reduced power consumption. The test results demonstrate an over 8-kV human-body-model ESD level and an over 13-A very fast transmission line pulse current level for charge-device-model ESD protection. The measured NF and power gain are 5.3 dB and 17.5 dB, respectively, at 58 GHz, under a power consumption of only 18 mW. To the best of our knowledge, the LC-based ESD-protected LNA demonstrates a highest ESD protection level with a lowest NF, compared with prior arts operating at similar frequencies.

A V-band self-healing power amplifier with adaptive feedback bias control in 65 nm CMOS

A self-healing two-stage 60 GHz power amplifier (PA) with amplitude/phase compensation is realized in 65 nm CMOS. An adaptive feedback bias scheme with three control knobs is proposed to extend the linear operating region and enhance chip-to-chip performance yield; allowing a 5.5 dB improvement of the output 1-dB compression point (P1dB) and a less than 2% chip-to-chip gain variation. At a 1 V supply, the fully differential PA achieves a saturation output power (Psat) of 14.85 dBm with a peak power-added-efficiency (PAE) of 16.2%. With the on-chip amplitude compensation, the P1dB is extended to 13.7 dBm. With the on-chip phase compensation, the output phase variation is minimized to less than 0.5 degree. To the best of our knowledge, this PA provides the highest Psat and P1dB with simultaneous high PAE for a single PA reported to date. The PA delivers a linear gain of 9.7 dB and has a 7 GHz bandwidth from 55.5 to 62.5 GHz with a very compact area of 0.042 mm2.

14.9 Sub-sampling all-digital fractional-N frequency synthesizer with −111dBc/Hz in-band phase noise and an FOM of −242dB

The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLLs high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.

A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration

A 5Gbps bi-directional RF-Interconnect (RF-I) with multi-drop and arbitration capabilities is designed and realized in 65nm CMOS. The baseband data are modulated in RF-I by using a 60GHz carrier in ASK format. An on-chip differential transmission line (TL) is used as the communication channel, which minimizes the latency (9ps/mm) only under the speed-of-light limitation. We insert λ/4 directional couplers for implementing multi-drops without signal reflection. We also use MOS switches along the signal path to reconfigure/arbitrate communication priority for multi-drops. This design consists of four TX/RX drops along a 5.5mm TL ring, supports destructive reading with fixed priority, and can reconfigure any drop as the transmitter. The tested data rate of the RF-I is 5Gbps with lower than 10-12 BER. The average power consumptions for the link are 1.33pJ/b and 0.24pJ/b/mm.