Jens Anders

A single-chip array of NMR receivers

We present the first single-chip array of integrated NMR receivers for parallel spectroscopy and imaging. The array, optimized for operation at 300 MHz, is composed of eight separate channels, with each channel consisting of a detection coil, a tuning capacitor, a low noise amplifier and a 50 ohm buffer. As all the integrated electronics are placed underneath the reception coils, the array is densely packed. Each single-channel reception coil has a diameter of 500 microm, resulting in a total active area of 1 mm by 2 mm for the array. The (1)H time-domain spin sensitivity of a single channel is approximately 1x10(15) spins/square root(Hz).

A fully integrated IQ-receiver for NMR microscopy

We present a fully integrated CMOS receiver for micro-magnetic resonance imaging together with a custom-made micro-gradient system. The receiver is designed for an operating frequency of 300 MHz. The chip consists of an on-chip detection coil and tuning capacitor as well as a low-noise amplifier and a quadrature downconversion mixer with corresponding low-frequency amplification stages. The design is realized in a 0.13 μm CMOS technology, it occupies a chip area of 950 × 800 μm² and it draws 50 mA from a supply voltage of 1.8 V. The achieved time-domain spin sensitivity is 5×10(14)spins/Hz. Images of phantoms obtained in our custom-made gradient system with 8 μm isotropic resolution are reported.

Integrated active tracking detector for MRI-guided interventions

We present a fully integrated detector suitable for active tracking of interventional devices in MR‐guided interventions. The single‐chip microsystem consists of a detection coil, a tuning capacitor, an intermediate frequency downconversion receiver, and a phase‐locked‐loop‐based frequency synthesizer. Thanks to the integrated mixer, the chip output stage delivers an analog frequency‐downconverted NMR signal in the frequency range from 0 to 200 kHz. The microchip, realized in a standard complementary metal oxide semiconductor technology, has a size of 1 × 2 × 0.74 mm3 and operates at a frequency of 63 MHz (i.e., in 1.5 T clinical scanners). Tests in a standard clinical scanner demonstrate the compatibility of the complementary metal oxide semiconductor microchip with clinical MRI systems. Using a solid sample of cis‐polyisoprene having a size of 1 × 1.9 × 0.8 mm3 as internal signal source, the detector achieves a three‐dimensional isotropic spatial resolution of 0.15 mm in a measuring time of 100 ms. Magn Reson Med, 2011.

A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC

A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 mum CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.

A GPU-Accelerated Web-Based Synthesis Tool for CT Sigma-Delta Modulators

This paper presents a design environment for continuous-time sigma-delta analog-to-digital converters for automatic coefficient scaling using a genetic algorithm. In order to provide an interactive design tool which enables the designer to transform and refine basic performance specifications into the desired, detailed high-level filter description, a short response time is mandatory. Previously published heuristic-search-based design tools have response times in the range of several ten minutes up to hours and are mostly not freely available. In contrast, the design environment presented in this paper provides results in less than a minute due the utilization of a fast simulation method implemented on a graphics card processor. Our hardware supported approach allows performing between 10 k and 67 k simulations and evaluations per second for internal model orders of one to eight, allowing to investigate millions of settings in less than a minute.

K-band single-chip electron spin resonance detector

We report on the design, fabrication, and characterization of an integrated detector for electron spin resonance spectroscopy operating at 27 GHz. The microsystem, consisting of an LC-oscillator and a frequency division module, is integrated onto a single silicon chip using a conventional complementary metal-oxide-semiconductor technology. The achieved room temperature spin sensitivity is about 10(8)spins/G Hz(1/2), with a sensitive volume of about (100 μm)(3). Operation at 77K is also demonstrated.

3D solenoidal microcoil arrays with CMOS integrated amplifiers for parallel MR imaging and spectroscopy

We present high-performance MR imaging and spectroscopy results obtained with wirebonded solenoidal microcoils manufactured in a MEMS-integrated technology. We report MR testing of 400µm inner diameter solenoidal microcoils for imaging of Eremosphaera Viridis algal cells with 10µm isotropic resolution. NMR spectroscopy has been performed on a water sample obtaining a linewidth of 0.04ppm. The newly introduced MEMS technology naturally lends itself to the fabrication of microcoil arrays, thus enabling parallel high-throughput MR investigation. As a proof of concept we report flip-chip integration of a microcoil-array with a CMOS amplifier array. “Teflon grease” has been used as phantom and three spectra have been acquired simultaneously yielding a linewidth of 0.5 kHz and a spin sensitivity in the frequency domain of 1015 spins/Hz½.

Room temperature strong coupling between a microwave oscillator and an ensemble of electron spins

We demonstrate theoretically and experimentally the possibility to achieve the strong coupling regime at room temperature with a microwave electronic oscillator coupled with an ensemble of electron spins. The coupled system shows bistable behaviour, with a broad hysteresis and sharp transitions. The coupling strength and the hysteresis width can be adjusted through the number of spins in the ensemble, the temperature, and the microwave field strength.

Cryogenic single-chip electron spin resonance detector

We report on the design and characterization of a single-chip electron spin resonance detector, operating at a frequency of about 20 GHz and in a temperature range extending at least from 300 K down to 4 K. The detector consists of an LC oscillator formed by a 200 μm diameter single turn aluminum planar coil, a metal-oxide-metal capacitor, and two metal-oxide-semiconductor field effect transistors used as negative resistance network. At 300 K, the oscillator has a frequency noise of 20 Hz/Hz(1/2) at 100 kHz offset from the 20 GHz carrier. At 4 K, the frequency noise is about 1 Hz/Hz(1/2) at 10 kHz offset. The spin sensitivity measured with a sample of DPPH is 10(8)spins/Hz(1/2) at 300 K and down to 10(6)spins/Hz(1/2) at 4 K.

A bidirectional neural interface with a HV stimulator and a LV neural amplifier

This paper shows a neural stimulator with 15V supply voltage combined with a neural low-noise amplifier (LNA) with a supply of ±1.65V around the common mode voltage (VCM) of 7.5V. In most implementations, the stimulator and recorder use the same supply domain, thus either leading to low voltage compliance (VC) for the stimulator or to high power consumption in the recorder. Obviously, a separation of both is the preferable choice, but comes with the challenge of effective protection of the low voltage (LV) sensitive input nodes of the recorder. A high voltage (HV) transistor used as a switch between the two parts enables different supply voltages for stimulator and recorder. Thus, a high current stimulator with high VC can be combined with a high efficient LV neural recorder. The presented implementation shows a stimulator with a maximum stimulation current of ±15mA with 5-bit resolution out of a 15V supply. The recording part consists of a LNA with a VCM of 7.5V and a supply voltage of ±1.65V around VCM - VDDLNA=9.15V and VSSLNA=5.85V. It consumes only 11.8μW and achieves an input referred root-mean-square (RMS) noise of 5.5μV in the frequency band of 1Hz to 100kHz. The design is implemented and simulated in a 0.18μm HV technology.