Ulrich Bihr

Evaluation study of compressed sensing for neural spike recordings

In this paper, an evaluation study of compressed sensing (CS) for neural action potential (spike) signals in MATLAB is presented. State-of-the-art neural recorders use 100 or more parallel channels to measure neural activity resulting in a data rate of 16 - 20 Mbit/s. Since a low-power design is required for an implanted neural recorder, it seems advantageous to compress the neural data prior to the wireless transmission. The continuous neural spike signals are compressed and transmitted to facilitate the possibility of an unrestricted data analysis at the receiver. Synthesized and recorded neural data sets are used to test the performance of CS. The 6-level Daubechies-8 wavelet decomposition matrix and two learned dictionary matrices are utilized as dictionaries for CS. The compression results are evaluated with the spike sorting program OSort. CS is shown to work for the compression of low-noise synthesized neural spike signals with a compression rate of 2.05, but cannot be recommended for the compression of neural spike signals in general.

Optical transcutaneous link for low power, high data rate telemetry

A low power and high data rate wireless optical link for implantable data transmission is presented in this paper. In some neural prosthetic applications particularly in regard to neural recording system, there is a demand for high speed communication between an implanted device and an external device. An optical transcutaneous link is a promising implantable telemetry solution, since it shows lower power requirements than RF telemetry. In this paper, this advantage is further enhanced by using a modified on-off keying and a simple custom designed low power VCSEL driver. This transmitter achieves an optical transcutaneous link capable of transmitting data at 50 Mbps through the 4 mm tissue, with a tolerance of 2 mm misalignment and a BER of less than 10-5, while the power consumption is only 4.1 mW or less.

A bidirectional neural interface with a HV stimulator and a LV neural amplifier

This paper shows a neural stimulator with 15V supply voltage combined with a neural low-noise amplifier (LNA) with a supply of ±1.65V around the common mode voltage (VCM) of 7.5V. In most implementations, the stimulator and recorder use the same supply domain, thus either leading to low voltage compliance (VC) for the stimulator or to high power consumption in the recorder. Obviously, a separation of both is the preferable choice, but comes with the challenge of effective protection of the low voltage (LV) sensitive input nodes of the recorder. A high voltage (HV) transistor used as a switch between the two parts enables different supply voltages for stimulator and recorder. Thus, a high current stimulator with high VC can be combined with a high efficient LV neural recorder. The presented implementation shows a stimulator with a maximum stimulation current of ±15mA with 5-bit resolution out of a 15V supply. The recording part consists of a LNA with a VCM of 7.5V and a supply voltage of ±1.65V around VCM - VDDLNA=9.15V and VSSLNA=5.85V. It consumes only 11.8μW and achieves an input referred root-mean-square (RMS) noise of 5.5μV in the frequency band of 1Hz to 100kHz. The design is implemented and simulated in a 0.18μm HV technology.

In vivo verification of a 100 Mbps transcutaneous optical telemetric link

We report on an optical telemetric link capable of providing a high data rate at a low power consumption for the transcutaneous transmission of neural signals. The telemetric link is designed for operation as the interface between an implanted cortical array and an external receiver. By converting the digitized neural signals to a stream of infrared optical pulses, the optical telemetry wirelessly transmits the neural data through the skin. The implantable transmitter prototype PCB contains a VCSEL (Vertical Cavity Surface Emitting Laser) driver with a VCSEL glued onto its chip surface. For protection, the transmitter PCB is coated with a thin layer of PDMS. The external receiver utilizes a large-size PIN silicon photodiode followed by a shunt shunt feedback transimpedance amplifier, a limiting amplifier and circuitry for clock and data recovery. In vivo tests performed on an anesthetized sheep show that the link is capable of transmitting data at a speed of 100 Mbps with a bit error rate (BER) of 2× 10-7 while consuming only 2.1 mW of electrical power.

A neural recorder IC with HV input multiplexer for voltage and current stimulation with 18V compliance

This paper presents an innovative ASIC design used in a high voltage (HV) neuromodulation system-in-package (SiP). A HV input switching network offers synchronous neural recording at 32 electrodes and independent stimulation on two selectable electrodes with up to 15mA and 18V input compliance. In addition, it provides artifact canceling and enables the use of different supply voltages for stimulator and recorder. Thus, a HV stimulator can be combined with a high efficient LV neural recorder design. Frequency separation of the local field potentials (LFP) and action potentials (AP) with individually adjustable gain and frequency settings via switched capacitor filter structures implicitly improves the input referred quantization error. The LFP low corner frequency can be measured reproducibly at 60mHz and the measured input referred noise is 3.3 μVrms for both, the AP and LFP band. The design is implemented in a 180nm HV CMOS technology, has a die size of 3.8mm × 4.3mm and a power consumption of 4.5mW.

A front-end circuit with active spike and LFP separation via a switched capacitor filter structure for neural recording applications

A fully differential front-end circuit for a neural recording system with spike and Local Field Potential (LFP) separation by means of switched capacitor (SC) filters is reported in this paper. In many neural recording chips the transmitter is the most power hungry element and defines the number of channels on a chip. With a separation of the neural signal, it is possible to reduce the data rate and so the power consumption of the transmitter without any reduction of resolution in the quantized signal. The system consists of a low-noise-amplifier (LNA), an anti-aliasing-filter with tunable gain and a corner frequency at 50kHz to enable SC circuits with a clock frequency of 100kHz. Two SC biquad filters with tunable gain and tunable corner frequency are implemented to split the spikes and the LFP from each other and to amplify the sub signals to the full swing. Both channels provide an input referred noise of 3.8μVrms in the passband and the whole front-end circuit has a power dissipation of 52μW. A prototype is fabricated in a standard 0.18μm CMOS process and tested successfully.

Recent advances in power efficient output stage for high density implantable stimulators

A major drawback of a current-controlled stimulation is its power efficiency. However, it is commonly used in implantable stimulators due to its safety. The power efficiency of a current-controlled stimulation can be improved by reducing the headroom voltage needed in the current driver. A promising technique is to bias the transistor in triode region whereas improving output impedance through the regulated cascode structure. This comes with a feature of implicit compliance monitor which is used for the supply voltage adaptation. This paper presents an overview on recent power efficient high voltage-compliance output drivers.

A bidirectional neural interface IC with high voltage compliance and spectral separation

This paper presents a fully integrated, bidirectional, neural interface, which is composed of a high voltage (HV) stimulator and a low voltage (LV) neural front-end with active, spectral separation. The stimulator uses a supply of ±9V in order to achieve a high voltage compliance (VC), whereas the recorder has a supply voltage of 3 V for high power efficiency. By using a HV transistor to separate the two parts, a safe operation of stimulator and recorder with different supply voltages can be guaranteed. Thereby the presented architecture can deliver a maximum stimulation current of ±10mA with a dynamic range of 50 dB and a VC of ±8.2 V. The implemented recording part consumes 52 μW and achieves a simulated input referred noise of 2.5μVrms in the low frequency band from 0.1 Hz to 200 Hz and 3.1 μVrms in the high frequency band from 200 Hz to 7.5 kHz. The combined recorder/stimulator requires 0.378 mm2 per channel. A prototype of the interface has been implemented and manufactured in a standard 0.18 μm HV CMOS technology.

Performance evaluation of a low power optical wireless link for biomedical data transfer

We report on an experimental low power transcutaneous optical telemetric link (TOTL) for high speed biomedical data transfer. By decreasing the bandwidth to data rate ratio, a silicon photodiode with large active size can be used to significantly increase transmission efficiency as well as misalignment tolerance. Additionally, a custom-designed transimpedance amplifier (TIA) with low input referred noise and a modified on-off keying with a custom designed low power VCSEL (vertical cavity surface emitting laser) driver are used to further reduce the required power consumption. The proposed system transmits data up to 75 Mbps through 6 mm thick tissue, in the presence of a 4 mm misalignment while achieving a BER better than 10-5, with a power consumption lower than 2.8 mW.

Wide-band efficiency-enhanced CMOS rectifier

We present in this paper the design of a wide-band efficiency-enhanced CMOS rectifier. A novel semi-active diode is proposed to minimize both the diode forward voltage drop and the reverse leakage current. This is achieved by dynamically configuring the rectification device as a threshold compensated diode in the on-state while a standard MOS diode in the offstate, respectively. The proposed rectifier is implemented in a 0.35μm 4M/2P standard CMOS process. In simulation, with 5.5V AC input at 13.56MHz, the rectifier outputs 4.94V DC voltage across a 1.2kΩ load resistor, achieving 87% power conversion efficiency (PCE) and 90% voltage conversion efficiency (VCE). The PCE and VCE can be maintained from 1MHz to 20MHz input frequency, with only 3% deviation in the PCE and 2% deviation in the VCE. In addition, the performance of the rectifier is self-compensated over temperature and process. From -40°C to +130°C, the simulated VCE varies within 2% from 89.6% to 87.7%, while the PCE stays almost constant at 86%. With 200 Monte Carlo samples, the standard deviation in the PCE and VCE are as low as 0.56% and 0.57%, respectively.