Jens Uwe Bruch

Investigation of systematical overlay errors limiting litho process performance of thick implant resists

Tapered resist profiles have been found to cause a deterimental effect on the overlay measurement capability, affecting lithography processes which utilize thick implant resist. Particularly, for resist thicknesses greater than 1.5 μm, the systematical contribution to the overlay error becomes predominant. In CMOS manufacturing, these resist types are being used mainly for high energy well implants. As design rules progressively shrink, the overlay requirements are getting tighter, such that the limits of the process capability are reached. Since the resist thickness cannot be reduced due to the requirements of the implant process, it becomes inevitable to reduce the systematical overlay error for the litho process involving thick resists. The following analysis concentrates on the tapers of overlay marks printed on thick i-line positive resists. Conventionally, overlay between two litho layers is measured from box in box marks with respect to a reference layer where the statistical shift between the boxes is expected to provide the biggest source of residuals. We observed however that an even bigger error could be introduced by an unevenness of the i-line resist tapers, adding asymmetrical chip magnification. The inclination of these tapers depends on the proximity and surface of the surrounding features and stack variations. We show that by adjusting soft and hard bake temperatures and times, tapers can be significantly reduced and thereby the overlay performance was greatly improved.

Overlay considerations for 300-mm lithography

Generally, the potential impact of systematical overlay errors on 300mm wafers is much larger than on 200mm wafers. Process problems which are merely identified as minor edge yield detractors on 200mm wafers, can evolve as major roadblocks for 300mm lithography. Therefore, it is commonly believed that achieving product overlay specifications on 300mm wafers is much more difficult than on 200mm wafers. Based on recent results on high volume 300mm DRAM manufacturing, it is shown that in reality this assumption does not hold. By optimizing the process, overlay results can be achieved which are comparable to the 200mm reference process. However, the influence of non-lithographic processes on the overlay performance becomes much more critical. Based on examples for specific overlay signatures, the influence of several processes on the overlay characteristics of 300mm wafers is demonstrated. Thus, process setup and process changes need to be analyzed monitored much more carefully. Any process variations affecting wafer related overlay have to be observed carefully. Fast reaction times are critical to avoid major yield loss. As the semiconductor industry converts to 300mm technology, lithographers have to focus more than ever on process integration aspects.