Jeong-Heon Park

Enhancement of data retention and write current scaling for sub-20nm STT-MRAM by utilizing dual interfaces for perpendicular magnetic anisotropy

We investigate the sub-20nm level scalability of STT-MRAM cells possessing perpendicular magnetization induced from the interface of free layer (FL) and MgO tunnel barrier. We demonstrate that the MTJs utilizing dual interfaces of FL and MgO exhibit enhanced scalability with high thermal stability and low switching current, compared with the MTJs with a single interface. As thermal stability factor (Δ) varies as a function of MTJ dimension, MTJs with dual interfaces show Δ over 60 at 20nm node, while MTJs of single interface show Δ around 33. MTJs with dual interface also exhibit lower switching current per thermal stability (Ic/Δ), ~1/2 level of single interface MTJs.

Dependence of Voltage and Size on Write Error Rates in Spin-Transfer Torque Magnetic Random-Access Memory

The dependence of the write-error rate (WER) on the applied write voltage, write pulse width, and device size was examined in individual devices of a spin-transfer torque (STT) magnetic random-access memory (MRAM) 4 kbit chip. We present 10 ns switching data at the 10-6 error level for 655 devices, ranging in diameter from 50 nm to 11 nm, to make a statistically significant demonstration that a specific magnetic tunnel junction stack with perpendicular magnetic anisotropy is capable of delivering good write performance in junction diameters range from 50 to 11 nm. Furthermore, write-error-rate data on one 11 nm device down to an error rate of 7×10-10 was demonstrated at 10 ns with a write current of 7.5 μA, corresponding to a record low switching energy below 100 fJ.

Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications

7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. AVT of 6T HD SRAM cell are 1.29 for PD (PG) and 1.34 for PU, respectively.