Jeong-Yun Lee

Inductively Coupled Pulsed Plasmas in the Presence of Synchronous Pulsed Substrate Bias for Robust, Reliable, and Fine Conductor Etching

Inductively coupled pulsed plasmas in the presence of synchronous pulsed substrate bias are characterized in a commercial plasma etching reactor for conductor etching. The synchronous pulsed plasma characteristics are evaluated through the following: 1) Ar-based Langmuir probe diagnostics; 2) Ar/Cl2 plasma modeling utilizing the hybrid plasma equipment model and the Monte Carlo feature model for the investigation of feature profile evolutions; 3) basic etching characteristics such as average etch rate and uniformity; 4) sub-50-nm Dynamic Random Access Memory (DRAM) basic etching performance and profile control; and 5) charge damage evaluation. It is demonstrated that one can control the etching uniformity and profile in advanced gate etching, and reduce the leakage current by varying the synchronous pulsed plasma parameters. Moreover, it is shown that synchronous pulsing has the promise of significantly reducing the electron shading effects compared with source pulsing mode and continuous-wave mode. The synchronous pulsed plasma paves the way to a wider window of operating conditions, which allows new plasma etching processes to address the large number of challenges emerging in the 45-nm and below technologies.

Effect of simultaneous source and bias pulsing in inductively coupled plasma etching

Pulsed rf plasmas show promise to overcome challenges for plasma etching at future technological nodes. In pulsed plasmas, it is important to characterize the transient phenomena to optimize plasma processing of materials. In particular, it is important to evaluate the effect of the ion energy and angular distribution (IEAD) functions during pulsing on etching of nanoscale features. In this work, the impact of simultaneous pulsing of both source and bias in an inductively coupled plasma on plasma characteristics and feature profile evolution is discussed using results from a two-dimensional reactor scale plasma model coupled to a Monte Carlo based feature profile model. Results are discussed for an Ar∕Cl2 gas mixture which is typically used for poly-Si etching. The consequences of duty cycle, pulse shape, and the phase lag between source and bias power pulses on discharge characteristics, IEADs to the wafer, and feature profile evolution are discussed. The low plasma density during the initial period of t...

Synchronous Pulse Plasma Operation upon Source and Bias Radio Frequencys for Inductively Coupled Plasma for Highly Reliable Gate Etching Technology

Synchronous pulse operation upon both source and bias RFs for inductively coupled plasma (ICP) etching system, having both dynamic matching networks and RF frequency-sweeping to ensure the lowest RF reflected power, is introduced for the first time. A superior performance of synchronous pulse operation to conventional continuous wave (cw) as well as source pulse operations is confirmed through plasma diagnostics by using Langmuir probe, plasma simulation by using hybrid plasma equipment model (HPEM) and etching performance. Significant reduction of RF power reflection during pulse operation as well as improvement of 35 nm gate critical dimension (CD) uniformity for sub-50 nm dynamic random access memory (DRAM) are achieved by adapting synchronous pulse plasma etching technology. It is definitely expected that synchronous pulse plasma system would have a great ability from a perspective of robustness on fabrication site, excellent gate CD controllability and minimization of plasma induced damage (PID) related device performance degradation.

Effect of the deposition geometry on the electrical properties within Tin- doped indium oxide film deposited under a given RF magnetron sputtering condition

Abstract Tin-doped indium oxide (ITO) film was deposited using RF-magnetron reactive sputtering and the electrical properties, such as resistivity, carrier concentration and mobility, were investigated as a function of the deposition position under a given magnetron sputtering condition. Non-homogeneity of the electrical properties was observed with the deposition position under a given magnetron sputtering condition. The resistivity of ITO thin film at the center of target had a minimum value, 2∼4×10−4 Ω cm, which increased when the substrate deviated from the center. ITO thin film deposited at the center had a maximum density of 7.0 g/cm3, which was a relative density of approximately 97% compared to the bulk. As the deposition position of ITO thin films deviated from the center, the density decreased. These experimental results clearly showed that non-homogeneity of the electrical properties with deposition position was due to the incidence angle, α, which had an atomic self-shadowing effect and also affected the film density. As the density of ITO thin film increased, both the mobility and conductivity increased with the same tendency. The mean free path increased with the density of ITO thin film and seemed to be saturated, while the grain size contracts with the variation of the mean free path. When the density of ITO thin films was close to the theoretical density, the mean free path was the same as the grain size (the distance between columns). However, in the other cases, the mean free path was smaller than the grain size. It is suggested that the scattering of free electrons at the grain boundary is the major factor for electrical conduction in ITO thin films having a high density, and other scattering sources, such as vacancies, holes, or pores, exist in ITO thin films having a low density.

Mechanism and CHARM2 Evaluation of P-Channel Metal Oxide Semiconductor Threshold Voltage Drop during High Density Plasma Heat-up Process

Plasma damage during the plasma deposition process is one of the most critical device characteristic issues facing complementary metal oxide semiconductor field effect transistor (CMOSFET) technology. In this paper, the CHARM2 monitoring system is used to evaluate UV damage and plasma charging damage during a high density plasma chemical vapor deposition (HDP-CVD) heat-up process. As a result, the amount of UV damage and negative charging damage is increased as the HDP-CVD heat-up process source power is increased. The main cause of P-channel metal oxide semiconductor field effect transistor (PMOSFET) threshold voltage drop is UV photon facilitated gate oxide electron trapping at the gate oxide and substrate P-channel interface during the HDP-CVD heat-up process. In N-channel metal oxide semiconductor field effect transistor (NMOSFET), when negative gate voltage stress is increased, gate oxide energy bend is flattened. Electrons cannot be trapped at the gate oxide and substrate N-channel interface. Therefore, the NMOSFET threshold voltage is constant during the HDP-CVD heat-up plasma process.