Ken Tokashiki

Inductively Coupled Pulsed Plasmas in the Presence of Synchronous Pulsed Substrate Bias for Robust, Reliable, and Fine Conductor Etching

Inductively coupled pulsed plasmas in the presence of synchronous pulsed substrate bias are characterized in a commercial plasma etching reactor for conductor etching. The synchronous pulsed plasma characteristics are evaluated through the following: 1) Ar-based Langmuir probe diagnostics; 2) Ar/Cl2 plasma modeling utilizing the hybrid plasma equipment model and the Monte Carlo feature model for the investigation of feature profile evolutions; 3) basic etching characteristics such as average etch rate and uniformity; 4) sub-50-nm Dynamic Random Access Memory (DRAM) basic etching performance and profile control; and 5) charge damage evaluation. It is demonstrated that one can control the etching uniformity and profile in advanced gate etching, and reduce the leakage current by varying the synchronous pulsed plasma parameters. Moreover, it is shown that synchronous pulsing has the promise of significantly reducing the electron shading effects compared with source pulsing mode and continuous-wave mode. The synchronous pulsed plasma paves the way to a wider window of operating conditions, which allows new plasma etching processes to address the large number of challenges emerging in the 45-nm and below technologies.

Effect of simultaneous source and bias pulsing in inductively coupled plasma etching

Pulsed rf plasmas show promise to overcome challenges for plasma etching at future technological nodes. In pulsed plasmas, it is important to characterize the transient phenomena to optimize plasma processing of materials. In particular, it is important to evaluate the effect of the ion energy and angular distribution (IEAD) functions during pulsing on etching of nanoscale features. In this work, the impact of simultaneous pulsing of both source and bias in an inductively coupled plasma on plasma characteristics and feature profile evolution is discussed using results from a two-dimensional reactor scale plasma model coupled to a Monte Carlo based feature profile model. Results are discussed for an Ar∕Cl2 gas mixture which is typically used for poly-Si etching. The consequences of duty cycle, pulse shape, and the phase lag between source and bias power pulses on discharge characteristics, IEADs to the wafer, and feature profile evolution are discussed. The low plasma density during the initial period of t...

Mechanism and CHARM2 Evaluation of P-Channel Metal Oxide Semiconductor Threshold Voltage Drop during High Density Plasma Heat-up Process

Plasma damage during the plasma deposition process is one of the most critical device characteristic issues facing complementary metal oxide semiconductor field effect transistor (CMOSFET) technology. In this paper, the CHARM2 monitoring system is used to evaluate UV damage and plasma charging damage during a high density plasma chemical vapor deposition (HDP-CVD) heat-up process. As a result, the amount of UV damage and negative charging damage is increased as the HDP-CVD heat-up process source power is increased. The main cause of P-channel metal oxide semiconductor field effect transistor (PMOSFET) threshold voltage drop is UV photon facilitated gate oxide electron trapping at the gate oxide and substrate P-channel interface during the HDP-CVD heat-up process. In N-channel metal oxide semiconductor field effect transistor (NMOSFET), when negative gate voltage stress is increased, gate oxide energy bend is flattened. Electrons cannot be trapped at the gate oxide and substrate N-channel interface. Therefore, the NMOSFET threshold voltage is constant during the HDP-CVD heat-up plasma process.