Jeonghyeon Cho

High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic RLGC equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases.

Through silicon via (TSV) equalizer

Through silicon via (TSV) is a promising vertical interconnection method to achieve a 3-dimensional integrated circuit (3D IC) system. However, high-speed digital signals suffer from severe distortions induced by TSV interconnects. In this paper, we propose a TSV equalizer using an ohmic contact on a double-sided silicon interposer to reduce the inter-symbol interference (ISI) of the TSV interconnects in a 3D IC system.

A Compact and Wide-Band Passive Equalizer Design Using a Stub With Defected Ground Structure for High Speed Data Transmission

A compact wide-band passive equalization design using a stub with defected ground structure is proposed. The proposed design, based on reflections under a slow wave effect, compensates for inter-symbol interference with wide bandwidth, compact size, remarkable compensation capability with few manufacturing limitations, and high design flexibility, compared to previous equalization design. Significant improvements in eye-opening and timing jitter are successfully demonstrated for a data rate of 8 Gbps for a 60 cm transmission line on a printed circuit board.

Accurate high frequency lossy model of differential signal line including mode-conversion and common-mode propagation effect

The loss in multilayer printed circuit boards (PCB) becomes a crucial problem and lacks precise models in high-speed interconnections such as the SerDes channel. Moreover, unbalanced and discontinuous structures generate undesirable mode-conversion, differential-to-common mode and common-to-differential mode. We have propose an accurate and efficient differential line model where all of the mode-conversion, common-mode propagation and frequency-dependent loss are taken into consideration over the GHz frequency range.

A Wide-Band Passive Equalizer Design on PCB Based on Near-End Crosstalk and Reflections for 12.5 Gbps Serial Data Transmission

We propose a wide-band passive equalization method for high-speed serial chip-to-chip input/output channels using wave propagation, reflection, and coupling effects on a tightly coupled transmission line structure. This design offers precise control of wideband equalization and low-power consumption as compared to previous active and discrete passive equalizers. Significant improvements in timing jitter and voltage margin are successfully demonstrated for a data rate of 12.5 Gbps on a 40 cm long backplane printed circuit board.

Mixed-Mode ABCD Parameters: Theory and Application to Signal Integrity Analysis of PCB-Level Differential Interconnects

The mixed-mode ABCD parameters are newly introduced and developed, where the definition and the connection are carefully established to have both the advantages of the mixed-mode S-parameters and the ABCD parameters, simultaneously. In addition, closed-form equations to model symmetric and asymmetric coupled transmission lines are derived. With the derived equations, the voltage transfer functions and the eye diagram of a variety of printed circuit board (PCB)-level differential interconnects are analytically attainable, which greatly enhances their applicability for signal integrity analysis. To verify the derived equations and to validate the proposed mixed-mode ABCD parameters, a series of microstrip-type differential lines on PCB test vehicles were fabricated and tested. The effectiveness of the proposed mixed-mode ABCD parameters was successfully confirmed through the comparison studies, in particular for the case of mode-conversion occurrence at the differential lines.

Modeling and Design Optimization of a Wideband Passive Equalizer on PCB Based on Near-End Crosstalk and Reflections for High-Speed Serial Data Transmission

We propose a closed-form analytic model for the newly presented passive equalizer using near-end crosstalk and reflections on printed circuit board (PCB). The proposed model is developed by using impulse response analysis and the Fourier transform. Based on the model, we propose a design-optimization procedure for the passive equalizer, which achieves eye-opening maximization and ISI minimization in order to maximize the equalization performance and reduce the design cycle. In the proposed optimization procedure, the eye-opening is maximized with a parameter sweep and peak distortion analysis, and the ISI is minimized by the proposed negative ISI cancellation technique. The proposed model and the design-optimization procedure are demonstrated experimentally for a data rate of 16 Gb/s on a 40-cm-long backplane PCB, and they achieve wideband equalization with a significant improvement in the voltage and timing margins of the received serial data.

A precise analytical eye-diagram estimation method for non-ideal high-speed channels

In this paper, we propose an analytical eye-diagram estimation method for a channel of a pair of differential microstrip traces on PCBs with arbitrary source and load terminations. The closed-form equation of the voltage transfer function for the given channel structure is derived and the method to deduce the worst case data patterns by considering the asymmetric and finite slew rates of the input signals is introduced. The validity of the proposed method was verified through comparison with the DDJ and eye-opening voltage values obtained by using HSPICE simulations.

Analysis of power/ground noise effect on performance degradation of analog-to-digital converter

This paper presents the analysis of the effect of power/ground noise on analog-to-digital converter (ADC). Power/ground noise is one of the noise sources to degrade ADC performance. Power distribution networks of off-chip and on-chip are modeled to analyze the mount of noise coupling and frequency response. Also, power/ground noise effect on ADC circuit is analyzed by spice simulation. It is analyzed and simulated that how noise coupled on power and ground can degrade designed flash ADC performance.

A fast and precise eye-diagram estimation method for a channel of a pair of differential microstrip lines on PCB with arbitrary terminations

In this paper, we propose a fast and precise eye-diagram estimation method for a channel of a pair of differential microstrip lines on PCBs with arbitrary source and load terminations. The voltage transfer function of a channel is investigated as a quick measure of the signal integrity of a channel and the DDJ and eye-opening voltage values are precisely estimated by using a modified peak distortion analysis. The efficiency and the accuracy of the proposed eye-diagram estimation method were successfully verified through HSPICE simulations.